• Title/Summary/Keyword: bit-by-bit algorithm

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Algorithm for Scaling of the Decoder inputs with Variable Transmission Rate (가변 전송율을 갖는 디코더 입력의 스케일링을 위한 알고리듬)

  • 진익수;심재영
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.5
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    • pp.887-892
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    • 2003
  • In this paper, we propose a simple scaling algorithm for CDMA mobile communications where a voice traffic signals are transmitted by individual one of several data rates at every frames. The traditional method is based on using look-up table called SMT(symbol metric table), but the proposed algorithm is real-time direct scaling method through simple bit manipulations without lookup table. The bit error rate performance is calculated by computer simulation over AWGN and Rayleigh fading channels. From the results, it is shown that the proposed algorithm outperforms the traditional SMT method on Rayleigh channel by 0.3∼0.8dB, while achieving the less H/W complexity.

Embedded One Chip Computer Design for Hardware Implementation of Genetic Algorithm (유전자 알고리즘 하드웨어 구현을 위한 전용 원칩 컴퓨터의 설계)

  • 박세현;이언학
    • Journal of Korea Multimedia Society
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    • v.4 no.1
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    • pp.82-90
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    • 2001
  • Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

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Real-time Implementation of Variable Transmission Bit Rate Vocoder Integrating G.729A Vocoder and Reduction of the Computational Amount SOLA-B Algorithm Using the TMS320C5416 (TMS320C5416을 이용한 G.729A 보코더와 계산량 감소된 SOLA-B 알고리즘을 통합한 가변 전송율 보코더의 실시간 구현)

  • 함명규;배명진
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.40 no.6
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    • pp.84-89
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    • 2003
  • In this paper, we real-time implemented to the TMS320C5416 the vocoder of variable bit rate applied the SOLA-B algorithm by Henja to the ITU-T G.729A vocoder of 8kbps transmission rate. This proposed method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. At this time, we bandied that the interval of cross correlation function if skipped every 3 sample for decreasing the computational amount of SOLA-B algorithm. The real-time implemented vocoder of C.729A and SOLA-B algorithm is represented the complexity of maximum that is 10.2MIPS in encoder and 2.8MIPS in decoder of 8kbps transmission rate. Also, it is represented the complexity of maximum that is 18.5MIPS in encoder and 13.1MIPS in decoder of 6kbps, it is 18.5MIPS in encoder and 13.1MIPS in decoder of 4kbps. The used memory is about program ROM 9.7kwords, table ROM 4.5kwords, RAM 5.1 kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, for evaluation of speech quality of the vocoder of real-time implemented variable bit rate, it is estimated the MOS score of 3.69 in 4kbps.

Improvement of Encoding Detection Algorithm for Multi-byte Encoded Data with Errors (오류가 발생한 멀티바이트 인코딩 데이터의 인코딩 기법 판별 알고리즘 개선)

  • Bae, Junwoo;Kim, Seonbeom;Park, Heejin
    • The Journal of Korean Institute of Next Generation Computing
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    • v.13 no.2
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    • pp.18-25
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    • 2017
  • In computer science, an encoding is a standardization of converting information to one format for audio, video or text. Therefore, the encoding information of the data should be known to open and read it and there are algorithms detecting encoder of the data. However, some informations of data could be disappeared by packet loss when transmitted on network, especially, if the data is snatched by packet sniffing or eavesdropping from wireless communications. In this paper, we improve the performance of encoding detection algorithm of 'uchardet' program for multi-byte encoded data with errors based on bit-shift algorithm. To simulate the performance, we generated Korean and Japanese text data with errors that is removed some random bits at random positions. Then the detection algorithm are tested using the data and 'uchardet-bitshift' showed better performance than 'uchardet'. When Korean texts are used, 'uchardet' could detect perfectly with ≤0.005% errors but it showed 0% detection rate with ≥1% errors while 'uchardet-bitshift' detected perfectly with ≤0.05% errors and it showed correct detection cases with ≥1% errors. Japanese texts with errors tend to report falsely as Chinese encoding because Japanese texts include lots of Chinese characters. As a results, we improved encoding detection algorithms by applying bit shift operation.

An Image Data Compression Algorithm by Means of Separating Edge Image and Non-Edge Image (윤곽선화상과 배경화상을 분리 처리하는 화상데이타 압축기법)

  • 최중한;김해수;조승환;이근영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.2
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    • pp.162-171
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    • 1991
  • This paper presents an algorithm for compressing image data by separating the image into two parts. I.e. edge image containing high-frequency components and non-edge image containing low-frequency components of image. The edge image is extracted by using 8 level compass gradient masks and the non-edge image is obtained by removing the edge image from the original image. The edge image is coded by Huffman run-length code and the non edge image is transformed first by DCT and the transformed images is coded next by a quantized bit allocation table. For an example image. GIRL. the proposed algorithm shows bit rate of 0.52 bpp with PSNR of 36dB.

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Adaptive Group Loading and Weighted Loading for MIMO OFDM Systems

  • Shrestha, Robin;Kim, Jae-Moung
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.11
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    • pp.1959-1975
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    • 2011
  • Adaptive Bit Loading (ABL) in Multiple-Input Multiple-Output Orthogonal Frequency-Division Multiplexing (MIMO-OFDM) is often used to achieve the desired Bit Error Rate (BER) performance in wireless systems. In this paper, we discuss some of the bit loading algorithms, compare them in terms of the BER performance, and present an effective and concise Adaptive Grouped Loading (AGL) algorithm. Furthermore, we propose a "weight factor" for loading algorithm to converge rapidly to the final solution for various data rate with variable Signal to Noise Ratio (SNR) gaps. In particular, we consider the bit loading in near optimal Singular Value Decomposition (SVD) based MIMO-OFDM system. While using SVD based system, the system requires perfect Channel State Information (CSI) of channel transfer function at the transmitter. This scenario of SVD based system is taken as an ideal case for the comparison of loading algorithms and to show the actual enhancement achievable by our AGL algorithm. Irrespective of the CSI requirement imposed by the mode of the system itself, ABL demands high level of feedback. Grouped Loading (GL) would reduce the feedback requirement depending upon the group size. However, this also leads to considerable degradation in BER performance. In our AGL algorithm, groups are formed with a number of consecutive sub-channels belonging to the same transmit antenna, with individual gains satisfying predefined criteria. Simulation results show that the proposed "weight factor" leads a loading algorithm to rapid convergence for various data rates with variable SNR gap values and AGL requires much lesser CSI compared to GL for the same BER performance.

Content-based Rate control for Hybrid Video Transmission (혼합영상 전송을 위한 내용기반 율제어)

  • 황재정;정동수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.8B
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    • pp.1424-1435
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    • 2000
  • A bit-rate controller that can achieve a constant bit rate when coding object-based video sequences is an important part to achieve an adaptation to bit-rate constraints, desired video quality, distribution of bits among objects, relationship between texture and shape coding, and determination of frame skip or not. Therefore we design content-based bit rate controller which will be used for relevant bit-rate control. The implementation is an extension of MPEG-4 rate control algorithm which employs a quadratic rate-quantizer model. The importance of different objects in a video is analyzed and segmented into a number of VOPs which are adaptively bit-allocated using the object-based modelling. Some test sequences are observed by a number of non-experts and interests in each object are analysed. The initial total target bit-rate for all objects is obtained by using the proposed technique. Then the total target bits are jointly analyzed for preventing from overflow or underflow of the buffer fullness. The target bits are distributed to each object in view of its importance, not only of statistical analysis such as motion vector magnitude, size of object shape, and coding distortion of previous frame. The scheme is compared with the rate controller adopted by the MPEG-4 VM8 video coder by representing their statistics and performance.

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An Efficient M-way Stream Join Algorithm Exploiting a Bit-vector Hash Table (비트-벡터 해시 테이블을 이용한 효율적인 다중 스트림 조인 알고리즘)

  • Kwon, Tae-Hyung;Kim, Hyeon-Gyu;Lee, Yu-Won;Kim, Myoung-Ho
    • Journal of KIISE:Databases
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    • v.35 no.4
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    • pp.297-306
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    • 2008
  • MJoin is proposed as an algorithm to join multiple data streams efficiently, whose characteristics are unpredictably changed. It extends a symmetric hash join to handle multiple data streams. Whenever a tuple arrives from a remote stream source, MJoin checks whether all of hash tables have matching tuples. However, when a join involves many data streams with low join selectivity, the performance of this checking process is significantly influenced by the checking order of hash tables. In this paper, we propose a BiHT-Join algorithm which extends MJoin to conduct this checking in a constant time regardless of a join order. BiHT-Join maintains a bit-vector which represents the existence of tuples in streams and decides a successful/unsuccessful join through comparing a bit-vector. Based on the bit-vector comparison, BiHT-Join can conduct a hash join only for successful joining tuples based on this decision. Our experimental results show that the proposed BiHT-Join provides better performance than MJoin in the processing of multiple streams.

Model-based Macroblock Layer Rate Control for Low Bit Rate Video Coding (저전송률 비디오 압축을 위한 모델 기반 매크로블록 레이어 비트율 제어)

  • Park, Sang-Hyun
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.4
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    • pp.50-57
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    • 2009
  • This paper presents a new model-based macroblock layer rate control algorithm for low bit rate video coding which generates output bits corresponding to a target bit budget. The H.264 standard uses various coding modes and optimization methods to improve the compression performance, which makes it difficult to control the generated traffic accurately in low bit rate environments. In the proposed scheme, we first estimate MAD values of macroblocks in a frame and define a target remaining bits using the estimated MAD values before encoding each macroblock. If a difference between the target value and the actual value is greater than a threshold value, the quantization parameter is adjusted to decrease the difference. It is shown by experimental results that the new algorithm can obtain more than 66% decrease of the difference between the target bits and the resulting bits for a frame with the PSNR performance better than that of the existing rate control algorithm.

Implementation of DCT using Bit Slice Signal Processor (BIT SLICE SIGNAL PROCESSOR를 이용한 DCT의 구현)

  • Kim, Dong-L.;Go, Seok-B.;Paek, Seung-K.;Lee, Tae-S.;Min, Byong-G.
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1449-1453
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    • 1987
  • A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

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