• Title/Summary/Keyword: bit rate

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A Study on 8kbps FBD-MPC Method Considering Low Bit Rate (Low Bit Rate을 고려한 8kbps FBD-MPC 방식에 관한 연구)

  • Lee, See-Woo
    • Journal of Digital Convergence
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    • v.12 no.6
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    • pp.271-276
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    • 2014
  • In a speech coding system using excitation source of voiced and unvoiced, it would be involved a distortion of speech quality in case coexist with a voiced and unvoiced consonants in a frame. In this paper, I propose a method of 8kbps Multi-Pulse Speech Coding(FBD-MPC: Frequency Band Division MPC) by using TSIUVC(Transition Segment Including Unvoiced Consonant) searching, extraction and approximation-synthesis method in a frequency domain. I evaluate the 8kbps MPC and FBD-MPC. As a result, SNRseg of FBD-MPC was improved 0.5dB for female voice and 0.2dB for male voice respectively. Compared to the MPC, SNRseg of FBD-MPC has been improved that I was able to control the distortion of the speech waveform finally. And so, I expect to be able to this method for cellular phone and smart phone using excitation source of low bit rate.

Design of a 3.3V 8-bit 200MSPS CMOS Folding/Interpolation ADC (3.3V 8-bit 200MSPS CMOS Folding/Interpolation ADC의 설계)

  • Na, Yu-Sam;Song, Min-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.3
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    • pp.198-204
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    • 2001
  • In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

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Research of QoS Control for Standardization on Real-time Multimedia Service Using MAC/PHY Feedback (MAC/PHY 정보를 이용한 실시간 멀티미디어 서비스의 QoS 제어 방식의 표준화를 위한 연구)

  • Kim, Min-Geon;Kim, Jun-Oh;Suh, Doug-Young
    • Journal of Broadcast Engineering
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    • v.16 no.5
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    • pp.738-749
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    • 2011
  • In this paper, we study QoS(Quality of Service) control protocols and the effect using MAC/PHY parameters of client device in mobile network. We proposes the way of controling the bit-rate by estimating the channel condition of the client with measured MAC/PHY parameters which is sent from the client. With the proposed method, more accurate available bit-rate can be estimated compared to conventional protocol, RTCP(Real-time Transport Control Protocol). The accurate bit-rate estimation can decrease wasted bit-rate and transport delay. In the result of the advantages, the transported video quality can be enhanced. In this paper, we show the effects of enhancement using client's the field data measured in WiMAX.

Design of a 1.2V 7-bit 800MSPS Folding-Interpolation A/D Converter with Offset Self-Calibration (Offset Self-Calibration 기법을 적용한 1.2V 7-bit 800MSPS Folding-Interpolation A/D 변환기의 설계)

  • Kim, Dae-Yun;Moon, Jun-Ho;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.18-27
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    • 2010
  • In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage,due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

Characteristics of Bit Error Rate dependence on the Position of Optical Phase Conjugator in 320 Gbps WDM System (320 Gbps WDM 전송 시스템에서 광 위상 공액기의 위치에 따른 비트 에러율 특성)

  • Lee Seong-Real
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.5
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    • pp.1123-1131
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    • 2005
  • In this paper, optimal position of optical phase conjugator (OPC) for best compensating distorted WDM channels due to both chromatic dispersion and self phase modulation (SPM) in $8{\times}40$ Gbps WDM systems is numerically investigated, and the eye opening penalty (EOP) and bit error rate (BER) characteristics of overall WDM channels at this position is investigated, comparing with that in case of OPC placed at mid-way of total transmission length. It is confirmed that the compensation extents in WDM system with OPC is more improved by the shifting OPC position from the mid-way of total transmission length, depending on the modulation format and fiber dispersion coefficient. Ant it is confirmed that, from a viewpoint of the reception performance, EOP of each channel is more or less different with one another, but the BER characteristics of overall channels are almost equal.

Effective Scalable Caching Algorithm by Minimizing Normalized Buffer Size over Constant-Bit-Rate Channel (일정한 채널 대역폭상에서 정규화 된 버퍼크기를 이용한 효율적인 선택적 캐슁 알고리즘)

  • Oh, Hyung-Rai;Song, Ywang-Jun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.8B
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    • pp.535-540
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    • 2005
  • This paper presents a scalable caching algorithm of proxy server with the finite storage size minimizing client's buffer size and constant-bit-rate channel bandwidth. Under the general video traffic condition, it is observed that the amount of decreased client's buffer size and channel bandwidth after caching a video frame depends on the relative frame position in the time axis as the frame size. Based on this fact, we propose an effective caching algorithm to select the cached frames by using the normalized buffer size. Finally, experimental results are provided to show the superior performance of the proposed alghrithm.

Adaptive Rate Control Based on Statistical Modeling in Frame-layer for H.264/AVC (H.264/AVC를 위한 통계 모델 기반 프레임 단위의 비트율 제어 기법)

  • Kim, Myoung-Jin;Hong, Min-Cheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.11C
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    • pp.917-928
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    • 2010
  • In this paper, we propose an efficient and adaptive rate control in Frame-layer for H.264/AVC. For given QP, bits according to video characteristics, and current frame is close correlation between the adjacent frames. Using the statistical characteristic, we obtain change of occurrence bit about QP to apply the bit amount by QP from the video characteristic and applied in the estimated bit amount of the each unit of current frame. In addition, we use weight with QP and occurrence bit amount that is statistical information of encoded previous frames. Simulation results show that the proposed rate control scheme could not only achieves time saving of more than 99% over existing rate control algorithm, but also increase the average PSNR of reconstructed video for around 0.02~0.43 dB in all the sequences.

Evaluation of Grade of WA-Vitrified and Resinoid Bond Grinding Wheels by Acoustic Emission (AE에 의한 WA계 비트리파이드 및 레지노이드 결합제 연삭숫돌의 결합도 평가)

  • Joung, In-Kuen;Lim, Young-Ho;Kwon, Dong-Ho
    • Journal of the Korean Society for Precision Engineering
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    • v.12 no.9
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    • pp.74-85
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    • 1995
  • The purpose of this paper is to evaluate the grade of WA vitrified and resinoid bond grinding wheels by the sue of AE measuring system. When the manufactured 48 kinds of specimens were scratched by the method of OKOSHI'S grade test, the relationship between the amount of bit scratch depth of grinding wheel specimens and the character- istics of AE signals, and the relationship of AE counts and grade were considered as fololws; (1) The higher the grades are AE cumlulative event counts N and AE event count rate n, the smaller the values tend to be. But A $E_{rms}$is in reverse. (2) In the case of same grade, the smaller the grain size is, the higher the value of AE cumulative event counts N and A $E_{rms}$is results of comparison and observation. The grinding wheel with lower elasticity and with higher percentage of pore detected higher value of AE cumula- tive event counts N than with higher elasticity and lower percentage of pore. But A $E_{rms}$ is in reverse. (3) AE cumulative event counts N and bit scratch depth h have normally one to one correspondence. (4) It can be expected that quantitative evaluations of grade by using AE have been carried out by the wave observation of AE signal in line with the relationship between load speed of bit and AE cumulative event counts N & AE event count rate n.' AE event count rate n.ate n.

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A Control of Channel Rate for Real-time VBR Video Transmission (실시간 비디오 전송을 위한 채널레이트 조절)

  • 고석주;이채영
    • Journal of the Korean Operations Research and Management Science Society
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    • v.24 no.3
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    • pp.63-72
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    • 1999
  • Recent studies on the Constant Bit Rate and Variable Bit Rate transmissions have mainly focused on the frame by frame encoder rate control based on the quantization parameter. With the existing approaches it is difficult to guarantee a consistent video quality. Also, the rate control overhead is too high for the real-time video sources. In this paper, a channel rate allocation scheme based on the control period is proposed to transmit a real-time video, in which the control period is defined by a pre-specified number of frames or group of pictures. At each control period, video traffic information is collected to determine the channel rate at the next control period. The channel rate is allocated to satisfy various channel rate constraints such that the buffer occupancy at the decoder is maintained at a target level. If the allocated channel rate approaches the level at which the negotiated traffic descriptions may be violated, the encoder rate is decreased through adjusting quantization parameters in the MPEG encoder. In the experimental results, the video quality and the overflow and underflow probabilities at the buffer are compared at different control periods. Experiments show that the video quality and the utilization of network bandwidth resources can be optimized through the suitable selection of the control period.

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BER Performance Analysis of Hierarchical-MPSK Using Phase Parameters (위상 파라미터 도출을 통한 H-MPSK의 BER 성능 분석)

  • Lee, Won-Joon;Park, Sang-Kyu
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.4
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    • pp.375-380
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    • 2009
  • Bit error rate(BER) performance of each bit for hierarchical M-ary phase shift keying(H-MPSK) modulation scheme is changed according to the phase parameters. Thus, a method to find the phase parameters appropriate to the requests of the system is needed. In this paper, we propose a method to obtain the phase parameters from an approximate approach of BER for H-MPSK and verify a validity of the proposed method through the previously provided expression for analyzing an exact error probability of H-MPSK.