• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.86-93
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• 1995

An optical transmitter was designed and implemented using a commercially available LiNbO$_{3}$ Mach-Zehnder modulator and the power amplifiers. We have adopted a new method to stabilize the bias voltage of the modulator using the second order harmonic component of the dithering signal. This technique has been applied successfully to the 2.5 Gbit/s external modulator for more than 6 hours without bit error rate degradaton. We demonstrated a repeaterless transmission of a 2.5 Gbit/s signal over 150 km nondispersion-shifted fiber using the transmitter. The receiver sensitivity was -34.5 dBm at 10$_{-10}$ bit error rate. No appreciable BER degradation due to fiber dispersion were observed after transmission.

• ETRI Journal
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• v.28 no.4
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• pp.533-536
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• 2006

A distributed Bragg reflector (DBR) laser and a high speed electroabsorption modulator (EAM) are integrated on the basis of the selective area growth technique. The typical threshold current is 4 to 6 mA, and the side mode suppression ratio is over 40 dB with single mode operation at 1550 nm. The DBR laser exhibits 2.5 to 3.3 mW fiber output power at a laser gain current of 100 mA, and a modulator bias voltage of 0 V. The 3 dB bandwidth is 13 GHz. A 10 Gbps non-return to zero operation with 12 dB extinction ratio is obtained. A four-channel laser array with 100 GHz wavelength spacing was fabricated and its operation at the designed wavelength was confirmed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.817-820
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• 2002

In this letter, we developed a 400Gb/s optical transmitter using an electroabsorption modulator and measured its characteristics. As a result, the extinction ratio, the output power and the wavelength are varied while DC bias voltage and temperature of an electroabsorption modulator are changed. Based upon these experimental results, a design of 400Gb/s optical transmitter can be optimized.

• ETRI Journal
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• v.28 no.3
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• pp.393-396
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• 2006

This letter proposes a new impedance matching scheme of a traveling wave electro-absorption modulator (TWEAM) module for a 60 GHz band radio-over-fiber (ROF) link. A microstrip band pass filter (BPF) was used to achieve impedance matching at the 60 GHz band, and termination resistance was carefully designed to obtain an input impedance close to $50\;{\Omega}$. Also, a bias circuit for the device was designed in the module. The measured return loss and frequency response show that the modulator module observes the characteristics of a filter without the need of a further tuning process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.854-861
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• 2008

We have described a high power hybrid envelope elimination and restoration(H-EER) transmitter for IEEE 802.16e Mobile World Interoperability for Microwave Access(WiMAX) using an efficiency optimized power amplifier(PA). The PA has been designed to have maximum PAE at the important power generation $V_{ds}$, region using Nitronex 100-W PEP GaN HEMT. For the high power application, H-EER transmitter should be considered the regenerative oscillation problem due to the PA's bias fluctuation effect and bias modulator stability issue. Therefore, the bias modulator for H-EER transmitter has been designed to suppress the regenerative oscillation. For the interlock experiment, the bias modulator has been built with the efficiency of 72% and peak output voltage of 30 V for the envelope signal with a PAPR of 8.5 dB. The H-EER transmitter for WiMAX application has been achieved a high PAE characteristic, 38.8 % at an output power of 41.25 dBm. By using digital predistortion(DPD) technique, the Relative Constellation Error (RCE) has been satisfied the specification of -34.5 dB. This is the first work at 2.655 GHz high power H-EER transmitter for WiMAX application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.221-224
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• 2012

This paper presents a CMOS interface circuit for MEMS acceleration sensor. It consists of a capacitance to voltage converter(CVC), a second-order switched-capacitor (SC) integrator and comparator. A bandgap reference(BGR) has been designed to supply a stable bias to the circuit and a ${\Sigma}{\Delta}$ Modulator with chopper - stabilization(CHS) has also been designed for more suppression of the low frequency noise and offset. As a result, the output of this ${\Sigma}{\Delta}$ Modulator increases about 10% duty cycle when the input voltage amplitude increases 100mV and the sensitivity is x, y-axis 0.45v/g, z-axis 0.28V/g. This work is designed and implemented in a 0.35um CMOS technology with a supply voltage of 3.3V and a sampling frequency of 3MHz sampling frequency. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.880-886
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• 2007

We have proposed a new "hybrid" envelope elimination and restoration(EER) transmitter architecture using an efficiency optimized power amplifier(PA) and modified bias modulator. The efficiency of the PA at the average drain voltage is very important for the overall transmitter efficiency because the PA operates mostly at the average power region of the modulation signal. Accordingly, the efficiency of the PA has been optimized at the region. Besides, the bias modulator has been accompanied with the emitter follower for the minimization of memory effect. A saturation amplifier, class $F^{-1}$ is built using a 5-W PEP LDMOSFET for forward-link single-carrier wideband code-division multiple-access(WCDMA) at 1-GHz. For the interlock experiment, the bias modulator has been built with the efficiency of 64.16% and peak output voltage of 31.8 V. The transmitter with the proposed PA and bias modulator has been achieved an efficiency of 44.19%, an improvement of 8.11%. Besides, the output power is enhanced to 32.33 dBm due to the class F operation and the PAE is 38.28% with ACLRs of -35.9 dBc at 5-MHz offset. These results show that the proposed architecture is a very good candidate for the linear and efficient high power transmitter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.42-42
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• 2001

본 논문은 주파수 천이를 적용시킨 광무선(fiber-radio)시스템의 광링크부에 대한 성능분석을 한다. 제시된 광링크부는 CS(control station)에서 얻어진 밀리미터파 대역 광파일럿톤(optical pilot tone)이 하향링크뿐 아니라 상향링크에도 공급되도록 하여 BS(base station)의 구조를 간단히 하였다. 광파일럿톤을 얻기 위해 CS의 EOM(electro-optic modulator)을 MAB(maximum bias), MIB(minimum bias), QB(quadrature bias)로 바이어스를 달리할 수 있으며 각각의 경우에 따라 링크의 성능을 분석한다. 분석은 레이저 광원의 전력이 일정한 경우와 PD(photo detector)에 수신되는 광 DC 전력이 일정한 경우에 대해서 행하여지며 각 경우에 대해서 최적의 하향링크 CNR 및 상향링크 SFDR(spurious free dynamic range)을 얻기 위해 효과적인 바이어스 방식을 제시한다