• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.96-105
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• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• Nuclear Engineering and Technology
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• v.54 no.10
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• pp.3803-3810
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• 2022

OpenMC is a community-driven open-source Monte Carlo neutron and photon transport simulation code. The Weight Window Mesh (WWM) function and an automatic Global Variance Reduction (GVR) method was recently developed and implemented in a developmental branch of OpenMC. This WWM function and GVR method broaden OpenMC's usage in general purposes deep penetration shielding calculations. However, the Local Variance Reduction (LVR) method, which suits the source-detector problem, is still missing in OpenMC. In this work, the Weight Window Generator (WWG) function has been developed and benchmarked for the same branch. This WWG function allows OpenMC to generate the WWM for the source-detector problem on its own. Single-material cases with varying shielding and sources were used to benchmark the WWG function and investigate how to set up the particle histories utilized in WWG-run and WWM-run. Results show that there is a maximum improvement of WWM generated by WWG. Based on the above results, instructions on determining the particle histories utilized in WWG-run and WWM-run for optimal computation efficiency are given and tested with a few multi-material cases. These benchmarks demonstrate the ability of the OpenMC WWG function and the above instructions for the source-detector problem. This developmental branch will be released and merged into the main distribution in the future.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.04a
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• pp.627-630
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• 1996

One of the most common communication mechanisms to describe a situation or a process is a story written as an ordered sequence of events or activities. For example, a shop floor supervisor may present the operations of his manufacturing system by describing the processes of manunfacturing a product in his shop. Although IDEF3 is one of the most commonly used methods for describing a business process, but it is not common for a manufacturing process. In this study, we tried to apply IDEF3 for describing a manufacturing process. Problems and suggestions such as selection probability, programmable process modeling, manufacturing resource model were presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1210-1230
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• 1997

In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.