• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.369-372
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• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.88-97
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• 1990

In this paper, DPA bus is proposed for implementation of MC 68000 based tightly-coupled multiprocessor system. The DPMC and arbiter are designed that the local memory of each PE can accept memory request both from a local processor and from the system bus. The performance of the proposed system bus is evaluated by Stochastic Petri Net(SPN) system modeling. The processing power, the efficiency, and the utilization of system bus are simulated for various load factors.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.149-154
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• 2000

시스템이 복잡해짐에 따라 현재 사용되고 있는 무작위적 테스트나 시뮬레이션은 프로토콜의 정확성을 확인하기에 충분하지 못하므로 보다 효율적이고 믿을 만한 검증 방법이 필요하다. 본 논문은 ETRI에서 개발한 디렉토리 기반 CC-NUMA시스템의 CCA(Cache Coherent Agent)보드 내부 버스인 I-Link(Inside Link) 버스의 중재 프로토콜을 정형 검증에 쓰이는 도구 중의 하나인 VIS(Verification Interacting with Synthesis)를 이용하여 검증한다. VIS는 Verilog 입력을 받는 도구이므로 개발 단계에서 만들어진 소스를 그대로 이용하여 검증하는 기법을 사용하였고 이를 통해 보다 정확한 명세와 검증을 할 수 있었다.

• Journal of Arbitration Studies
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• v.16 no.3
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• pp.91-125
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• 2006

The arbitration rule of CIETAC was vastly revised and was put in force on May 1, 2005. By its revision, China has improved its arbitration system. Chinese arbitration law had many problems when it was enacted in 1995, but the problems could not be avoided because of the poor surroundings for arbitration in China. As China has not had much experience in operating its legal system effectively, and also has little in the way of studies on legal theory that would allow it to deal with its laws in a flexible manner, authorities usually wait to revise a law until enough relevant experience has been accumulated. Therefore, during the 10 years since its enactment, China has resolved the problems within its arbitration law through revision of arbitration rule rather than by revision of the law itself. As this law is a basic one in ruling the arbitration system in China, there are some limitations as to how far the system can be developed through revision of arbitration rule alone. In spite of the limitations, the revision in 2005 contributed a great deal to resolving the existing problems within Chinese arbitration law. The biggest problem in the arbitration law is the Chinese arbitration law that restricts party autonomy. With the revision of the arbitration rule, many problems concerning party autonomy were circumvented. This occurred because the arbitration rule now provides parties the opportunity to choose arbitration rule other than the CIETAC arbitration rule, and even allows parties to agree to amend articles in the CIETAC arbitration rule -- a very important revision indeed. In addition to party autonomy, there are other improvements for example, there is an enhancement of the independent character of the CIETAC, clearing of jurisdiction, easing in the formation of arbitration agreement, improvement in the way arbitrators are chosen, and enhancement in the cultural neutrality of the arbiter. Problems still remain that can only be solved by revision of the arbitration law itself. These problems relate to the governing law of the arbitration agreement, the collection of evidence, custody of property, selection of chief arbiter, interlocutory awards, etc. In addition, some non-legal problems must also be resolved, like the actual judicial review of arbitration awards or difficulties of executing arbitration awards.

• Journal of the Korea Institute of Building Construction
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• v.13 no.5
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• pp.498-505
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• 2013

The main processes involved in a defect dispute are consulting, reviewing, and finally judging as an arbiter. This process of defect consulting produces a defect consulting report, but business practices and standards of judgment will differ among consultants, and have many problems. This study reviews the structure of a defect consulting report and considers the structure's problem, which is that it is not standardized. To achieve this, data of sixteen defect consulting report were collected involving defect lawsuit cases before or after 2010. The structure and index of the defect consulting reports were then reviewed, and the results are as follows. As for a structure based on fourteen index, there are suitable that judge a outline, a cost estimate data and a consulting work item by a consulting standard. Furthermore, analysis by each common parts and private parts is considered as appropriate about consulting items and estimate by standard. However, consulting item in construction progress and responsibility period for security that related on a cause and a responsibility of defect need to complement. Meanwhile, the first thing of issues are connected a defect consulting is urgent a standardization for a defect type.

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.12
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• pp.2632-2640
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• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2025-2035
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• 2014

The read range of UHF mobile readers can be extended by a booster for mobile RFID readers (BoMR). But in an environment where multiple BoMRs are installed, the read success rate may be decreased due to signal interference. This paper proposes three arbitration methods based on interference estimation with the purpose of enhancing the read success rate. A central arbitration server manages global information in centralized arbitration method (CAM) without broadcast/multicast communication facility. In fully distributed arbitration method (FDAM), all the arbitration messages are broadcasted from a BoMR to every BoMR, and each BoMR decides with broadcasted global information. Events in FDAM are serialized naturally with broadcasted messages. Cluster Distributed Arbitration Method (CDAM) forms clusters with multicasted BoMRs and a selected BoMR acts as an arbiter in the cluster. Such effects as lengthened read range, improved the read success rates of readers can be obtained by the proposed methods without any hardware modification. In order to evaluate the arbitration methods, the RFID system is modeled by using the DEVS formalism and simulated by using the DEVSim++.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.264-267
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• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.