• 한국통신학회:학술대회논문집
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• 한국통신학회 1987년도 춘계학술발표회 논문집
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• pp.219-222
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• 1987

A Semi-cusion VLSI Digital Filter Design for TDM/FDM tran-smultiplexer is decribed. Using the polyphase network approach a filter bank composed of only all-pasdigital filter sections was designed. The use of all-pass filters as basic building blocks is shown to provide a Transmultiplexer structure that has low computational requirements low quanization noise and hign modularity. A design of 1st order 2nd All pass filter is done using COMS 2um double metal.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.850-853
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• 1987

A VLSI digital filter design using a semi-custom method is described. The digital filters composed of TDM/FDM Transmultiplexer are designed. Using the polyphase network approach a filter bank composed of only all-pass digital filter sections was designed. The use of all-pass filters as basic building blocks is shown to provide a transmultiplexer structure that has low computational requirements, low quantization noise, and high modularity. The silicon compiler systems is used to reduce the design time and increase the credibility of designed filters. A design of 1st order and 2nd order all pass filters is done using CMOS 2um N-well double metal cell.

• 대한전자공학회논문지
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• 제25권2호
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• pp.227-232
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• 1988

A semicustom VLSI design fo digital filters used in TDM/FDM transmultiplexer is described. A filter bank composed of only all-pass digital filter sections are implemented with the polyphase network. The use of all-pass filters as basic building blocks is shown to provide a trans-multiplexer structure that has low computational requirements, low quantization noise, and high modularity. The silicon compiler system is used to reduce the design time and to increase the credibility of designed filters. As a prototype, 1st and 2nd order all pass filter are designed, using CMOS N-well double metal technology. The chip sizes of first order filter and the second order filter are 2652 x 533\ulcorner\ulcorner 5334x4300\ulcorner\ulcorner respectively.

• 한국산업정보학회논문지
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• 제19권2호
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• pp.45-49
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• 2014

In this work, a phase shifter radio-frequency integrated chip (RFIC) using a simple all-pass network is presented. As a tuning element of the phase shifter RFIC, tunable capacitors with a multi-layer dielectric of a para-/ferro-/para-electrics using a high tunable BST ferroelectric and a low-loss BZN paraelectric thin film were utilized. In order to evaluate and analyze the fabricated phase shifter RFIC, the same elements such as an inductor and capacitor integrated into it are also fabricated and tested. The designed phase shifter RFIC was fabricated on a quartz substrate in the size of $1.16{\times}1.21mm^2$. As the test results, the maximum phase difference of $350^{\circ}$ is obtained at 15 V and its tuning frequency bandwidth is 90 MHz from 2.72 to 2.81GHz.

• 대한전자공학회논문지SP
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• 제43권5호
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• pp.62-71
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• 2006

최근에 모바일 기기와 같은 적은 메모리를 요구하는 환경에 적합한 인공잔향기의 개발이 이슈화 되고 있다. 이러한 조건에 적합한 한가지 방법은 콤 필터의 궤환루프안에 시간변화 전대역통과 필터(APF)를 삽입하는 것이다. 본 논문에서는 시간변화 APF를 사용하는 잔향기의 이론적, 지각적 분석을 시행함으로써 지각적으로 수용 가능한 APF의 페이즈 변화량을 찾았다. 그리고 이를 바탕으로 새로운 시간변화 잔향기 설계 방법을 제안한다. 제안된 잔향기의 성능평가를 통해 제안된 잔향기가 적은 메모리를 사용하면서도 기존의 시불변 잔향기와 동일한 성능을 보임을 확인하였다.

• 한국전자파학회논문지
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• 제22권1호
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• pp.114-124
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• 2011

본 논문에서는 2 GHz 선형 위상 천이 특성을 갖는 위상천이기를 설계 및 제작하여 보였다. 소형의 위상 천이기 구현을 위해 집중소자로 구성된 전통과 회로망(all pass network)을 기반으로 위상천이기를 구성하고, 박막세라믹 공정을 이용하여 제작하였다. 또한, 선형의 위상 천이 특성을 얻기 위해 버랙터(varactor) 다이오드에 직렬 커패시터를 연결하여, 전압에 대한 커패시턴스를 선형화함으로써 비선형성을 개선하였다. 전통과 회로망에 나타나는 인덕터는 스파이럴 인덕터로 구현하고, 이를 다이오드 바이어스 회로에 활용하여 $4\;mm{\times}4\;mm$ 면적을 가지는 소형 위상천이기를 구성할 수 있었다. 또한, 온-웨이퍼(on wafer)로 측정을 위해 입출력은 CPW(Coplanar Waveguide) 형상으로 구현하였으며, 제작된 위상천이기는 버랙터 조정 전압 0~5 V에 대하여, 2 GHz에서 삽입 손실은 약 4.2~4.7 dB, 위상 변화량은 약 $79^{\circ}$였으며, 예상한대로 선형 위상 천이 특성을 보였다.

• 한국광학회지
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• 제33권3호
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• pp.106-112
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• 2022

이중 링 add/drop 필터와 all-pass 지연 필터로 구성된 이차원 optical code division multiple access (OCDMA) 인코더/디코더를 제안하고, 설계 예시 및 수치해석을 통하여 실현 가능성을 확인하였다. 제안된 OCDMA 인코더/디코더의 칩 면적은 지연 도파로를 사용하는 기존 OCDMA 인코더/디코더에 비하여 1/3 정도로 줄어든다. 제안된 소자의 성능을 모델링하기 위하여 고속 푸리에 변환(fast Fourier transform, FFT) 및 전달 행렬 기법을 사용하였다. 정확한 코드로 디코딩된 펄스의 중심에서 자기상관 피크 값은 어긋난 파장 호핑 코드 및 스펙트럼 위상 코드로 디코딩된 경우의 최대 교차상관 레벨에 비하여 3배 이상으로 관측되었다. 이를 통하여 forward error correction (FEC) 한계에 해당하는 10^-3 이하의 비트 에러 오율을 얻을 수 있음을 알 수 있다.

• Journal of information and communication convergence engineering
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• 제4권4호
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• pp.166-169
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• 2006

Almost all network systems provide an authentication mechanism based on user ID and password. In such system, it is easy to obtain the user password using a sniffer program with illegal eavesdropping. The one-time password and challenge-response method are useful authentication schemes that protect the user passwords against eavesdropping. In client/server environments, the one-time password scheme using time is especially useful because it solves the synchronization problem. In this paper, we present a new identification scheme: OPI(One Pass Identification). The security of OPI is based on the square root problem, and OPI is secure: against the well known attacks including pre-play attack, off-line dictionary attack and server comprise. A number of pass of OPI is one, and OPI processes the password and does not need the key. We think that OPI is excellent for the consuming time to verify the prover.

• Journal of information and communication convergence engineering
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• 제16권2호
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• pp.84-92
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• 2018

For large wireless sensor networks running on battery power, the time synchronization of all sensor nodes is becoming a crucial task for waking up sensor nodes with exact timing and controlling transmission and reception timing. However, as network size increases, this synchronization process tends to require long processing time consume significant power. Furthermore, a naïve synchronization scheduler may leave some nodes unsynchronized. This paper proposes a power-efficient scheduling algorithm for time synchronization utilizing the notion of density, which is defined by the number of neighboring nodes within wireless range. The proposed scheduling algorithm elects a sequence of minimal reference nodes that can complete the synchronization with the smallest possible number of hops and lowest possible power consumption. Additionally, it ensures coverage of all sensor nodes utilizing a two-pass synchronization scheduling process. We implemented the proposed synchronization algorithm in a network simulator. Extensive simulation results demonstrate that the proposed algorithm can reduce the power consumption required for the periodic synchronization process by up to 40% for large sensor networks compared to a simplistic multi-hop synchronization method.

• 전기학회논문지
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• 제58권11호
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• pp.2281-2285
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• 2009

Powerline communication is the data signal which is modulated by carrier frequency through the installed powerline at in-home or office is transmitted and received signals are separated into data signal with using band-pass filter which cent-frequency is carrier frequency. The home gateway, an equipment which works as an gateway for ubiquitous home network, relays all functions of a home network. The home gateway must always be connected in order to provide seamless services. However it gives unfavorable power consumption. Therefore the needs for working in maximum power saving mode while there is no data traffic and for invoking to the normal function when it is necessary. So, in this paper we survey the development of low power PLC modem monitoring of power consumption and breaking abnormal power in the home Network.