• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2005년도 ISMP
• /
• pp.201-212
• /
• 2005

[ $Epoxy/BaTiO_3$ ] composite embedded capacitor films (ECFs) were newly designed fur high dielectric constant and low tolerance (less than ${\pm}15\%$) embedded capacitor fabrication for organic substrates. In terms of material formulation, ECFs are composed of specially formulated epoxy resin and latent curing agent, and in terms of coating process, a comma roll coating method is used for uniform film thickness in large area. Dielectric constant of $BaTiO_3\;&\;SrTiO_3$ composite ECF is measured with MIM capacitor at 100 kHz using LCR meter. Dielectric constant of $BaTiO_3$ ECF is bigger than that of $SrTiO_3$ ECF, and it is due to difference of permittivity of $BaTiO_3\;and\;SrTiO_3$ particles. Dielectric constant of $BaTiO_3\;&\;SrTiO_3$ ECF in high frequency range $(0.5\~10GHz)$ is measured using cavity resonance method. In order to estimate dielectric constant, the reflection coefficient is measured with a network analyzer. Dielectric constant is calculated by observing the frequencies of the resonant cavity modes. About both powders, calculated dielectric constants in this frequency range are about 3/4 of the dielectric constants at 1 MHz. This difference is due to the decrease of the dielectric constant of epoxy matrix. For $BaTiO_3$ ECF, there is the dielectric relaxation at $5\~9GHz$. It is due to changing of polarization mode of $BaTiO_3$ powder. In the case of $SrTiO_3$ ECF, there is no relaxation up to 10GHz. Alternative material for embedded capacitor fabrication is $epoxy/BaTiO_3$ composite embedded capacitor paste (ECP). It uses similar materials formulation like ECF and a screen printing method for film coating. The screen printing method has the advantage of forming capacitor partially in desired part. But the screen printing makes surface irregularity during mask peel-off, Surface flatness is significantly improved by adding some additives and by applying pressure during curing. As a result, dielectric layer with improved thickness uniformity is successfully demonstrated. Using $epoxy/BaTiO_3$ composite ECP, dielectric constant of 63 and specific capacitance of 5.1nF/cm2 were achieved.

• 마이크로전자및패키징학회지
• /
• 제24권1호
• /
• pp.35-43
• /
• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• 국제학술발표논문집
• /
• The 8th International Conference on Construction Engineering and Project Management
• /
• pp.201-206
• /
• 2020

Diversification of project delivery methods (PDM) under ever-changing construction business environment has significantly changed the role of project participants. Active efforts to effectively sharing the roles and responsibilities have been observed in the project management offices (PMOs) among owner/operator organizations as well as engineering, procurement, construction and maintenance (EPCM) firms. In order for being effective in a holistic way throughout the project life-cycle, a PMO needs to have 'adequate management skills' as well as 'essential technical capabilities' in cooperating with many different participants. One of the well-known examples of the PMO's tool to support these skills and capabilities is the effective 'work packaging (WP)' that serves as a common basis integrating all relevant information in a structured manner. In an attempt to enhance the construction productivity, the concept of 'advanced work packing (AWP)' has been introduced by Construction Industry Institute (CII). The AWP enables productivity to be improved by early planning of construction packages in the design phase "with the end in mind". The purpose of this study is to identify and evaluate the 'variables' of advanced work packing (AWP) for life-cycle information integration. Firstly, an extended concept of advanced WP based on the CII AWP was defined in order to comprehend many different issues of business functions (e.g. cost, schedule, quality, etc.). A structured list of major components and variables of AWP were then identified and examined for practical viability with real-world examples. Strategic fits and managerial effectiveness were stressed throughout the analyses. Findings, implications and lessons learned are briefly discussed as well.

• 마이크로전자및패키징학회지
• /
• 제12권3호
• /
• pp.187-196
• /
• 2005

MEMS에서 제조 공정 오차 및 외부 응력은 진동형 자이로스코프와 같은 MEMS 소자의 제조 수율에 많은 영향을 미친다. 특히 비연성 진동형 자이로스코프의 경우 감지모드와 구동모드의 주파수 차의 특성은 수율에 직접적인 영향을 미친다. SOI (Silicon-On-Insulator) 공정 및 양극접합 공정으로 패키징된 자이로스코프의 경우, 노칭현상으로 인하여 구조물이 불균일하게 가공되며, 동시에 열팽창계수 차로 인하여 접합된 기판에 큰 휨이 발생한다. 그 결과주파수 차의 분포가 커지고, 동시에 수율은 저하되었다. 이를 개선하기 위하여 SiOG (Silicon On Glass) 기술을 적용하였다. SiOG 공정에서는 접합 후에 기판의 휨을 최소화 하기 위하여 1장의 실리콘 기관과 2장의 유리 기판을 사용하였으며, 노칭을 방지하기 위하여 금속 박막을 사용하였다. 그 결과 노칭 현상이 방지되었으며, 기판의 휨도 감소하였다. 또한 주파수 차의 분포도 매우 균일하게 되었으며, 주파수 차의 편차 또한 개선이 되었다. 그 결과 높은 수율 및 보다 강건한 MEMS 자이로스코프를 개발할 수 있었다.

• 한국레이저가공학회지
• /
• 제17권3호
• /
• pp.15-18
• /
• 2014

In this paper, we studied a machining method using a diffractive beam splitter (DBS) and multi- pulse repeated radiation for breathable film. We fabricated micro-grooves on polypropylene (PP) films using multi-pulse radiation and one-shot radiation (radiating pulses at once) and a DBS. In the result, width and depth of the PP film using multi-pulse repeated radiation were more precisely controllable. Therefore, this method can be applicable to in manufacturing breathable film precisely at a high speed.

• 멤브레인
• /
• 제25권2호
• /
• pp.85-98
• /
• 2015

고분자의 용이한 가공성과 우수한 투명성, 그리고 합리적인 비용 효율로 인해 식품 포장 산업에서 금속이나 유리용기들을 고분자 기반의 포장 소재들로 대체하려는 경향이 전 세계적으로 널리 퍼지고 있다. Barrier 고분자들은 산소, 이산화탄소, 수증기 등 대기 가스에 대한 낮은 투과성을 나타내고 있어 식품 포장 산업 이용에 유용하다. 이러한 식품 포장 산업의 전반적인 추세와 함께, 산소에 민감한 주스, 착향 음료, 그리고 에너지 음료 등 새로운 식품 산업의 성장으로 인해 고성능의 barrier 특성, 특히 $O_2$와 $CO_2$에 대해 낮은 투과성을 지닌 고분자 포장 소재의 개발이 시급한 상황이다. 기존의 고분자에 기반한 barrier의 성능 향상은 새로운 식품 포장 산업에 급격한 변화를 줄 것이다. 본 총설에서는 (1) antiplasticization을 유도한 barrier 소재들, (2) antiplasticization과 crystallization을 사용한 barrier 성능 상승 효과, (3) 새로운 barrier 고분자들, (4) 나노합성 소재, (5) 혼합 고분자 등과 더불어, 차세대 포장 소재들의 특성 분석을 소개하고자 한다.

• International Journal of Advanced Culture Technology
• /
• 제12권1호
• /
• pp.116-122
• /
• 2024

The growth of the national economy and the improvement of household consumption have had a profound impact on the design of children's food packaging. As household economic conditions improve, children's consumption needs and habits are becoming more diverse. Especially in the field of children's food, food packaging still plays a key role, not only to protect the freshness and safety of food, but also to create a pleasant and fun emotional atmosphere in the minds of children. The aim of this study is to explore the close link between emotional interaction and the children's food market, and to study approaches to children's food packaging design to provide beneficial insights to promote sales and meet changing consumer needs.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
• /
• pp.53-58
• /
• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• 마이크로전자및패키징학회지
• /
• 제30권3호
• /
• pp.1-10
• /
• 2023

최근, 고사양 컴퓨터, 모바일 제품의 수요가 증가하면서 반도체 패키지의 고집적화, 고밀도화가 요구된다. 따라서 많은 양의 데이터를 한 번에 전송하기 위해 범프 크기 및 피치 (Pitch)를 줄이고 I/O 밀도를 증가시킬 수 있는 플립 칩 (flip-chip), 구리 필러 (Cu pillar)와 같은 마이크로 범프 (Micro-bump)가 사용된다. 하지만 범프의 직경이 70 ㎛ 이하일 경우 솔더 (Solder) 내 금속간화합물 (Intermetallic compound, IMC)이 차지하는 부피 분율의 급격한 증가로 인해 취성이 증가하고, 전기적 특성이 감소하여 접합부 신뢰성을 악화시킨다. 따라서 이러한 점을 개선하기 위해 UBM (Under Bump Metallization) 또는 Cu pillar와 솔더 캡 사이에 diffusion barrier 역할을 하는 층을 삽입시키기도 한다. 본 review 논문에서는 추가적인 층 삽입을 통해 마이크로 범프의 과도한 IMC의 성장을 억제하여 접합부 특성을 향상시키기 위한 다양한 연구를 비교 분석하였다.

• 대한용접접합학회:학술대회논문집
• /
• 대한용접접합학회 2002년도 Proceedings of the International Welding/Joining Conference-Korea
• /
• pp.439-449
• /
• 2002

This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.