• Journal of Korean Society for Quality Management
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• v.23 no.4
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• pp.128-147
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• 1995

An accelerated life testing(ALT) for aluminum electrolytic capacitors is conducted and analyzed. A testing equipment, which consists of part fixtures, relay board, controller, video bridge and microcomputer, is made for the ALT. Load factors are temperature with four levels and voltage with three levels. Base on 'optimized 4:2:1 plan', 2,000 electrolytic capacitors are allocated at 12 experimental conditions(; 4 levels of temperature ${\times}3$ levels of voltage), and the ALT is conducted. From the experimental results, an acceleration model is derived and acceleration factors are estimated. A discussion on the experimental results is included.

• 한국신재생에너지학회:학술대회논문집
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• 2005.11a
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• pp.673-676
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• 2005

To design the effective usage of electric double layer capacitors (EDLCs) used for a storage device of dye sensitized solar cell(DSC) energy, we first investigated the accumulation state of electrical charges and the charge behavior in the EDLCs. Based on the results. the voltage characteristics of EDLCs connected to DSC energy were evaluated. The results showed that the charge accumulation region concentrated on central part of the carbonaceous electrode in EDLCs and the required times for charging and discharging were almost the same.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.171-174
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• 2001

This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance .value is changed by the polarity of current or voltage. and this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit id constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduce and the power factor improve. A circuit design method is shown by experimentation and confirmed simulation. It explained that compared conventional pulse width modulated (PWM) inverter with half pulse-width modulated (HPWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Journal of Power Electronics
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• v.18 no.4
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• pp.997-1006
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• 2018

This paper proposes a transformerless photovoltaic (PV) power converter system based on the DC/AC boost inverter, which can solve the leakage current and second-order ripple power issues in single-phase grid-connected PV inverters. In the proposed topology, the leakage current can be decreased remarkably since most of the common-mode currents flow through the output capacitor, by-passing parasitic capacitors, and grounding resistors. In addition, the inherent ripple power component in the single-phase grid inverter can be suppressed without adding any extra components. Therefore, bulky electrolytic capacitors can be replaced by small film capacitors. The effectiveness of the proposed topology has been verified by simulation and experimental results for a 1-kW PV PCS.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.7
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• pp.59-66
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• 2013

This paper proposes a new voltage reference generation method for Four-Switch Inverters(FSI) with compensation of the neutral DC-link voltage variation. Since FSIs have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, it is required to take account the voltage difference between the top and bottom capacitors. In this paper, to reduce the effect by the voltage variation, reference voltages are modified by adding compensation voltages proportional to the voltage difference between upper and lower capacitors. Simulation results showing control performance of induction and permanent magnet motors demonstrate the validity of the proposed method.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1044-1048
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• 2001

This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. This paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit id constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduce and the power factor improve. A circuit design method is shown by experimentation and confirmed simulation. It explained that compared conventional pulse-width modulated (PWM)inverter with half pulse-width modulated (HPWM) inverter proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.368-369
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• 2006

Ferroelectric thin films have attracted much attention for applications in nonvolatile ferroelectric random access memories(NVFeRAM) from the view points of high speed operation, low power consumption, and large scale Integration[1,2]. Among the FRAM, BLT is of particular interest. as it is not only crystallized at relatively low processing temperature, but also shows highly fatigue resistance and large remanent polarization Meanwhile, these submicron ferroelectric capacitors were fabricated by a damascene process using Chemical mechanical polishing (CMP). BLT capacitors were practicable by a damascene process using CMP. The P-E hysteresis were measured under an applied bias of ${\pm}5V$ by using an RT66A measurement system. The electric properties such as I-V were determined by using HP4155A analysers.

• ETRI Journal
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• v.28 no.4
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• pp.486-494
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• 2006

Two current-mode and/or voltage-mode quadrature oscillator circuits each using one fully-differential second-generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current-mode quadrature signals have the advantage of high-output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current-mode and voltage-mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.6
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• pp.242-248
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• 2006

This paper proposes a coordinated control method for under-load tap changers (ULTCs) with shunt capacitors to reduce the operation numbers of both devices. The proposed method consists of two stages. In the first stage, the dispatch schedule is determined using a genetic algorithm with forecasted loads to reduce the power loss and to improve the voltage profile during a day. In the second stage, each capacitor operates according to this dispatch schedule and the ULTCs are controlled in real time with the modified reference voltages considering the dispatch schedule of the capacitors. The performance of the method is evaluated for the modified IEEE 14-bus system. Simulation results show that the proposed method performs better than a conventional control method.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2795-2797
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.