• Proceedings of the Korea Society of Information Technology Applications Conference
• /
• 2005.11a
• /
• pp.331-334
• /
• 2005

This paper suggests the Ethernet aggregation to XGMII framing procedure (EAXFP) mechanism to economically combine the traffic adaptation technology with the link aggregation method in designing 10 Gigabit Ethernet (10 GbE) interfaces. This design sidesteps the data-loss issues that can result from designing an interface with only one link. The most critical issue in relation to the link aggregation interface is the algorithm used to control frame distribution between the ten ports. The proposed EAXFP mechanism offers an efficient link aggregation method as well as an efficient frame distribution algorithm, which maximize the throughout of the 10 GbE interface. In the experiment and analysis of the proposed mechanism, it was also discovered that the 10 GbE interface that uses the proposed EAXFP mechanism significantly reduced the packet loss rate. When there will be heavy traffic loads come about in the future, the proposed EAXFP mechanism assures an efficient and economical transmission performance on the router system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.5
• /
• pp.812-820
• /
• 2006

Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique(not only LAN, but MAN and WAN) to ethernet. Performance evaluation was performed using C language for 10Gbps ethernet Data Link to design the optimum hardware, then internal FIFO size was evaluated. In this paper, MAC core for 10Gbps ethernet which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMII interface block was designed using VHDL language and Xilinx 6.2i tool and verified using Model_SIM 5.7G simulator. According to the specification of 10Gbps ethernet, MAC core with 64-bit data path should support 156.25MHz in order to support 10Gbps. The designed MAC core that process 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps data processing. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.

• Proceedings of the IEEK Conference
• /
• 2003.07a
• /
• pp.378-381
• /
• 2003

This paper presents a design and implementation of 10gigabit ethernet frame multiplexer/demultiplexer. In this paper, we discuss gigabit and 10 gigabit ethernet standard interfaces(GMII/XGMII) and we propose multiple gigabit ethernet frame multiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then 10gigabit ethernet frame MUX/DMUX is designed, verified and implemented using FPGA.