• Journal of Computing Science and Engineering
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• 제3권4호
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• pp.195-215
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• 2009

Worst-case execution time (WCET) analysis is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. While significant progress has been made for WCET analysis of instruction caches, the data cache timing analysis, especially for set-associative data caches, is rather limited. This paper proposes an approach to safely and tightly bounding data cache performance by computing the worst-case stack distance of data cache accesses. Our approach can not only be applied to direct-mapped caches, but also be used for set-associative or even fully-associative caches without increasing the complexity of analysis. Moreover, the proposed approach can statically categorize worst-case data cache misses into cold, conflict, and capacity misses, which can provide useful insights for designers to enhance the worst-case data cache performance. Our evaluation shows that the proposed data cache timing analysis technique can safely and accurately estimate the worst-case data cache performance, and the overestimation as compared to the observed worst-case data cache misses is within 1% on average.

• Journal of Communications and Networks
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• 제6권1호
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• pp.78-87
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• 2004

This paper presents deterministic, worst-case analysis of a queueing system whose multiple homogeneous input streams are regulated by the associated leaky buckets and the queueing system that has a single stream regulated by the jumping-window. Queueing delay averaged over all items is used for performance measure, and the worst-case input traffic and the worst-case performance are identified for both queueing systems. For the former queueing system, the analysis explores different phase relations among leaky-bucket token generations. This paper observes how the phase differences among the leaky buckets affect the worst-case queueing performance. Then, this paper relates the worst-case performance of the former queueing system with that of the latter (the single stream case, as in the aggregate streams from many users, whose item arrivals are regulated by one jumping-window). It is shown that the worst-case performance of the latter is identical to that of the former in which all leaky buckets have the same phase and have particular leaky bucket parameters.

• 항공우주기술
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• 제7권2호
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• pp.58-66
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• 2008

우주 환경에서 동작하는 위성의 전자회로를 설계할 때는 지상에서 동작하는 상용 회로 설계와는 다른 고려 요소들이 존재한다. 그 이유는 첫째, 위성은 우주 방사능 등에 직접적으로 노출된 우주 환경에서 동작하기 때문이고, 둘째, 한번 궤도로 올라간 위성에 대해서 수리나 노화에 따른 교체가 불가능하기 때문이다. 이러한 상황에서 주어진 임무 기간 동안 아무런 문제없이 임무를 잘 수행하는 전자회로를 설계하기 위해서는 지상에서 동작하는 회로의 Worst Case Analysis보다 훨씬 엄격한 조건의 WCA를 적용해야 한다. 본 논문에서는 ESA에서 제시하는 WCA에 관한 규격서인 ECSS-Q-30-01A에서 WCA를 위해 고려해야할 입력요소들과 WCA 적용 방법을 정리하고, 실제로 저궤도 On-Board Computer에 구현된 간단한 회로를 가지고 WCA 적용 사례를 제시하고자 한다.

• Journal of Computing Science and Engineering
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• 제5권2호
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

• 항공우주기술
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• 제8권1호
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• pp.162-171
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• 2009

위성 전자회로의 다양한 전압을 생성하는 선형 전압 조절기는 우주 방사능에 강인한 칩을 사용하기도 하지만, 간단한 선형 전압 조절기 회로를 구현하여 사용하는 경우가 많다. 이때, 설계한 선형 전압 조절기는 공급할 전압에 따라 조금씩 다른 형태로 설계할 수 있지만, 회로 설계에 따른 최악 조건 해석은 일관된 방법론과 체크해야할 항목으로 정리될 수 있다. 본 논문에서는 일반적인 재래식 선형 전압 조절기 회로에서 수행할 최악 조건 해석 방법을 기술하고, 정리한다.

• Journal of Computing Science and Engineering
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• 제5권1호
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• pp.1-18
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• 2011

As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

• 한국산업융합학회 논문집
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• 제20권3호
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• pp.205-212
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• 2017

This paper focuses on worst-case delay analysis of the time-triggered IEEE 802.15.4 protocol to satisfy the industrial quality-of-service (QoS) performance. The IEEE 802.15.4 protocol is considered to be unsuitable for industrial networks because its medium access control method is contention-based CSMA/CA, which exhibits unstable performance with an unbounded delay distribution under heavy traffic. To avoid these limitations, this paper presents a time-triggered version of the nonbeacon-enabled network of IEEE 802.15.4 that relies on a time division multiplexing access (TDMA) method implemented in the application layer without any modification of specification. The timing analysis of this time-triggered IEEE 802.15.4 was executed, and the worst-case transmission delay was calculated. Based on this analysis, the time-triggered IEEE 802.15.4 is a promising alternative for wireless industrial networking.

• 한국자동차공학회논문집
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• 제10권5호
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• pp.114-120
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• 2002

In a distributed real-time control system, it is essential to confirm the timing behavior of all tasks because these tasks of each real-time controller have to finish their processes within the specified time intervals called a deadline. In order to satisfy this objective, the timing analysis of a distributed real-time system such as shcedulability test must be performed during the system design phase. In this study, a simple application of CAN fur a vehicle body network system is formulated to apply to a holistic scheduling analysis, and the worst-case execution time (WCET) and the worst-case end-to-end response time (WCRT) are evaluated in the point of holistic system view.

• 대한전자공학회논문지
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• 제25권6호
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• pp.637-646
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• 1988

The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

• 대한기계학회논문집
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• 제13권3호
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• pp.554-560
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• 1989

본 연구에서는 실제 운행시에 발생할 수 있는 최악의 경우를 모든 반기의 무게를 집중질량으로 고려한 충실한 해석을 통하여 구해보고자 하였다. 이를 위하여 하나의 구간에 여러 개의 집중질량이 달린 경우에 대한 선로방정식을 유도하였고, 최소반력을 구하기 위한 문제를 최적설계 문제로 정의한 다음, 이를 체험적 최적설계 기법(heuristic optimization technique)을 통하여 해결하였다. 또한 예재해석을 통하여 최악의 상태가 발생하게 될 일반적인 조건을 구하였다.