• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.859-867
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• 2010

In this paper, we propose some parallel structures of the word-based nonlinear combining functions in word-based stream cipher, high-speed versions of general (bit-based) nonlinear combining functions. Especially, we propose the high-speed structures of popular four kinds in word-based nonlinear combiners using by PS-WFSR (Parallel-Shifting or Parallel-Structured Word-based FSR): m-parallel word-based nonlinear combiner without memory, m-parallel word-based nonlinear combiner with memories, m-parallel word-based nonlinear filter function, and m-parallel word-based clock-controlled function. In addition, we propose an implementation example of the m-parallel word-based DRAGON stream cipher, and determine its cryptographic security and performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.383-386
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• 2009

In this paper, we propose some parallel structures of the word-based nonlinear combine functions in word-based stream cipher, high-speed versions of general (bit-based) nonlinear combine functions. Especially, we propose the high-speed structures of popular three kinds in word-based nonlinear combiners using by PS-WFSR (Parallel-Shifting or Parallel-Structured Word-based FSR): m-parallel word-based nonlinear combiner without memory, m-parallel word-based nonlinear combiner with memories, and m-parallel word-based nonlinear filter function. Finally, we analyze its cryptographic security and performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1702-1708
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• 2007

Dragon Stream Cipher is proposed for software base implementation in the eSTREAM project. Now this stream cipher is selected as a phase 3 focus candidate. Dragon is a new stream cipher contructed using a single word based NIFSR(non-linear feed back shift register) and 128/256 key/IV(Initialization Vector). Dragon is the keystream generator that produce 64bits of keystream. In this paper, we present an implementation of Drag(m stream cipher algorithm in hardware. Finally, the implementation is on Altera FPGA device, EP3C35F672I and the timing simulation is done on Altera's Quartus II. A result of 111MHz maximum clock rate and 7.1Gbps is throughput is obtained from the implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1519-1527
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• 2007

In order to combat the security threats that sensor networks are exposed to, a cryptography protocol is implemented at sensor nodes for point-to-point encryption between nodes. Given that nodes have limited resources, symmetric cryptography that is proven to be efficient for low power devices is implemented. Data protection is integrated into a sensor's packet by the means of symmetric encryption with the Dragon stream cipher and incorporating the newly designed Dragon-MAC Message Authentication Code. The proposed algorithm was designed to employ some of the data already computed by the underlying Dragon stream cipher for the purpose of minimizing the computational cost of the operations required by the MAC algorithm. In view that Dragon is a word based stream cipher with a fast key stream generation, it is very suitable for a constrained environment. Our protocol regarded the entity authentication and message authentication through the implementation of authenticated encryption scheme in wireless sensor nodes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2164-2170
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• 2011

Rapid surge in date quantity lead to increase in storage demand from corporate. The existing SAN with fiber channel is being changed to IP-based SAN environment due to installment and maintenance cost. But the IP-based network still have some similar security problems as existing TCP/IP network. Also, for the security reasons of storage traffic, data are encrypted, but with the existing system, data larger than 10G can't be handled. To address security and speed issue, this paper proposes to a structure applied to IP SAN environment with Parallel Structure Word-based FSR (PS-WFSR) as hardware.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.1-5
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• 2011

Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.