• The Journal of the Korean dental association
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• v.48 no.5
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• pp.391-406
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• 2010

Orthodontic treatment for middle-aged patients has become more commonplace with various reasons including improved socioeconomic status. Understanding of oral status and treatment modalities of middle-aged patients is mandatory for accurate diagnosis and proper treatment planning. This study investigated 100 consecutive patients aged 40s and 50s and 100 aged 20s who had been examined and diagnosed at the Department of Orthodontics, Chonnam National University Dental Hospital. The results were obtained as follows; 1. Gender distribution showed female outnumbered male patients in young-aged adult patients, but middle-aged patients showed similar male and female distribution. 2. The major concern seeking orthodontic treatment was esthetics not only in young-aged but also in middle-aged adult patients, and a number of middle-aged patients were concerned about oral health as well. 3. Considerable number of middle-aged patients were referred by other dental specialties while young-aged adult patients were more self-motivated for orthodontic treatment. 4. Middle-aged adult patients had more missing teeth and periodontal disease than young-aged adults. 5. The most frequently-observed problem was dental spacing in middle-aged patients while dental crowding in young-aged adult patients. Middle-aged patients showed higher prevalence of deep overbite and overjet while most of young-aged adults presented opposite direction of problem in overbite and overjet. 6. Limited orthodontic treatment was required rather than comprehensive treatment in middle-aged patients, and the most common tooth moving area was anterior part of dentition in case of limited treatment. Need of interdisciplinary therapy with other dental specialties was more common in middle-aged patients. 7. Intervention of specific technique such as invisible TP, passive bracketing, passive wire bonding, and lingual orthodontics was more required in middle-aged patients. Considering that middle-aged patients have different characteristics than young-aged adults, the results of the present study suggest that different treatment modalities are required in middle-aged orthodontic patients in order to manage them properly and efficiently.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• International Journal of Highway Engineering
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• v.3 no.4 s.10
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• pp.117-126
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• 2001

In this research, evaluation of adhesion in tension property of SBR-modified concrete to ordinary portland cement concrete was conducted with uniaxial direct tensile bond test which was proposed by Kuhlmann. A test set-up was fabricated in order to minimize the eccentric force by introducing a joint which might fully rotate. The main experimental variables were cement-latex ratios, surface preparations and moisture levels. The results obtained were as follows: The LMC specimen at 15% latex-cement ratio increased the adhesion in tension by range of 37% compared to that of conventional cement concrete. This might be due to latex film formed between cement paste and aggregate. The effects of surface preparation on bond of latex modified concrete to conventional concrete were significant at the conditions by sand paper and wire brush. A better bond could be achieved by rough surface rather than smooth. The saturated and surface dry (SSD) condition were considered to be the most appropriate moisture level followed by wet, finally by dry. Thus, a proper surface preparation and moisture level are quite necessity in order to obtain better bonding at LMC overlay.

• Tunnel and Underground Space
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• v.23 no.5
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• pp.413-427
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• 2013

Thin Spray-on Liners(TSLs) based on polymer materials have been considered as an alternative to shotcrete and wire mesh in relatively fair rock conditions, and used in mines since 1990s. Nevertheless, Few experimental studies on their mechanical properties necessary for the evaluation of their bearing capacities as a support member have been carried out. In this study, tensile and bond strengths of two kinds of TSLs with different material compositions were measured at the age of 7 days. In addition, two kinds of bending tests proposed by EFNARC (2008) to simulate representative failure mechanisms of TSLs were carried out on the same materials and curing age as in tension and pull-out tests. From the tests, tensile strength of a TSL is shown to increase as its content of polymer is higher. In contrast, its bond strength seems to be in inverse proportion to its polymer content. Especially, the TSL material in which a cementitious component is included with relatively smaller polymer content shows a faster hardening characteristic which results in higher resistance to de-bonding between a TSL and a substrate. As a result, it is shown that the performance of TSLs might be dependent upon its corresponding polymer content.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1228-1238
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• 2012

In this paper, we design, fabricate and measure two kinds of high-frequency packages for K-band CMOS FMCW radar chips using RF via structures. The packages are fabricated with the conventional PCB process and LTCC process. The design centering of the packages is performed at 24 GHz and impedance variation caused by the wire bonding and RF via structure is fully evaluated using 3D electromagnetic simulation. The RF via structure with characteristic impedance of $50{\Omega}$ is used to reduce impedance mismatch loss. Two kinds of test packages with back-to-back connected RF paths are fabricated and measured for the design verification of the PCB-based package and LTCC package. Their measured results show an insertion loss of less than 0.4 dB at 24 GHz and less than 0.5 dB for 20~29 GHz. The measured return loss is less than -13 dB for the PCB-based package and less than -15 dB for the LTCC package in the frequency band, but the return loss of the package itself is predicted to be better than that of the test package by about 5 dB, because the ripples of the back-to-back connection typically degrade the return loss by 5 dB or more.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.25-29
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• 2022

Recently, the importance of electronic packaging technology has been attracting attention, and heterogeneous integration technology in which chips are stacked out-of-plane direction is being applied to the electronic packaging field. The 2.5D integration circuit is a technology for stacking chips using an interposer including TSV, and is widely used already. Therefore, it is necessary to make the interposer mechanically reliable in the packaging process that undergoes various thermal processes and mechanical loadings. Considering the structural characteristics of the interposer on which several thin films are deposited, thermal stress due to the difference in thermal expansion coefficients of materials can have a great effect on reliability. In this study, the mechanical reliability of the metal pad for wire bonding on the silicon interposer against thermal stress was evaluated. After heating the interposer to the solder reflow temperature, the delamination of the metal pad that occurred during cooling was observed and the mechanism was investigated. In addition, it was confirmed that the high cooling rate and the defect caused by handling promote delamination of the metal pads.