• Proceedings of the KIPE Conference
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• 전력전자학회 2016년도 추계학술대회 논문집
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• pp.155-156
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• 2016

• Proceedings of the KIPE Conference
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• 전력전자학회 2018년도 추계학술대회
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• pp.209-210
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• 2018

• Journal of Ocean Engineering and Technology
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• 제22권2호
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• pp.65-71
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• 2008

Recently, many researches in relation to data transmission with faster speed and greater volume, many researches have been carried out on sonar systems for underwater communication. According to these researches, an acoustic transducer for underwater communication requires wide bandwidth properties. In domestic researches for underwater communication sonar, an operating frequency in the range of $20{\sim}40\;kHz$ is used. In this paper, we propose anon-resonance type acoustic transducer for underwater communication. The TVR (transmitting voltage response) characteristics increased linearly as the frequency increased, and the RVS (receiving voltage sensitivity) characteristics were constant as the frequency increased. Traditional techniques for wide bandwidth transducershave a limit and a transmission loss difference at lower and higher frequency operating ranges. In this paper, the new transducer proposed decreased the transmission loss under some conditions. It was optimized with the FE analysis tool (ATILA) and evaluated using the TVR and the RVS characteristics in the range of $10{\sim}90\;kHz$. The value of TVR was 138 dB at 20 kHz and 148 dB at 40 kHz, and the differences was 12 dB. The value of RVS was $195{\pm}2\;dB$ and nearly constant. From theseresults, it is certain that the developed transducers can be used for an underwater communication network in the 1.3 km range with both a 20 kHz bandwidth and 30 kHz center frequency.

• ETRI Journal
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• 제31권5호
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• pp.576-584
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• 2009

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• Journal of Power Electronics
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• 제13권4호
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• pp.592-599
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• 2013

This paper investigates a new isolated single-phase AC-DC converter, which integrates a modified AC-DC buck-boost converter with a DC-DC forward converter. The front semi-stage is operated in discontinuous conduction mode (DCM) to achieve an almost unity power factor and a low total harmonic distortion of the input current. The rear semi-stage is used for step-down voltage conversion and electrical isolation. The front semi-stage uses a coupled inductor with the same winding-turn in the primary and secondary sides, which is charged in series during the switch-on period and is discharged in parallel during the switch-off period. The discharging time can be shortened. In other words, the duty ratio can be extended. This semi-stage can be operated in a larger duty-ratio range than the conventional AC-DC buck-boost converter for DCM operation. Therefore, the proposed converter is suitable for universal input voltage (90~264 $V_{rms}$) and a wide output-power range. Moreover, the voltage stress on the DC-link capacitor is low. Finally, a prototype circuit is implemented to verify the performance of the proposed converter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.198-206
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• 2013

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ${\mu}m$ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ${\mu}m$ process and the die area of the solenoid inductor is 0.013 $mm^2$. The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

• Journal of electromagnetic engineering and science
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• 제5권1호
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• pp.8-13
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• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제35C권11호
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• pp.57-62
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• 1998

In this paper, tunable transconductor shows good linearity over a wide input voltage range are proposed. The proposed transconductor employ operating in the nonsaturation(ie., linear) region to improve circuit simplicity and tunability and 6.8V$\_$p-p/ wide input range. Also the circuit employ source-coupled differential pair to provide true differential input and can achieve both positive and negative transconductance values. The proposed circuits are implemented using a 1.2 $\mu\textrm{m}$ single poly double metal n-well CMOS technology. The THD characteristic of proposed circuit is less than 1% for a differential input voltage of up to 6V$\^$p-p/ when supply bias condition is V$\_$DD/=-V$\_$ss/=5V, I$\_$B/=20, 40${\mu}$A, and frequency of input signal is 1KHz.

• Journal of Power Electronics
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• 제16권3호
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• pp.970-981
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• 2016

Leakage currents occur in pulse-width-modulated voltage source inverter (PWM-VSI)-fed permanent magnet synchronous motor (PMSM) drives for air-conditioners, which seriously affect system safety and operation performance. High accuracy modeling and prediction of leakage currents are key issues for the design and implementation of air-conditioning products. In this study, the generation mechanism of leakage currents is discussed. A systematic modeling approach of leakage currents is proposed, including the modeling of leakage current sources and leakage current paths. By using the proposed approach, the complete model of leakage currents in PWM-VSI-fed PMSM drives for air-conditioners has been developed based on the extraction of all parameters. A comparison between the simulated leakage currents based on the developed model and measured leakage currents in the outdoor unit of an air-conditioning product is conducted. The comparison verifies the effectiveness of the proposed modeling approach, and the developed model exhibits high accuracy within a wide frequency range.