• Title/Summary/Keyword: WiMAX Architecture

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On the QoS Behavior of Self-Similar Traffic in a Converged ONU-BS Under Custom Queueing

  • Obele, Brownson Obaridoa;Iftikhar, Mohsin;Kang, Min-Ho
    • Journal of Communications and Networks
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    • v.13 no.3
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    • pp.286-297
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    • 2011
  • A novel converged optical network unit (ONU)-base station (BS) architecture has been contemplated for next-generation optical-wireless networks. It has been demonstrated through high quality studies that data traffic carried by both wired and wireless networks exhibit self-similar and long range dependent characteristics; attributes that classical teletraffic theory based on simplistic Poisson models fail to capture. Therefore, in order to apprehend the proposed converged architecture and to reinforce the provisioning of tightly bound quality of service (QoS) parameters to end-users, we substantiate the analysis of the QoS behavior of the ONU-BS under self-similar and long range dependent traffic conditions using custom queuing which is a common queuing discipline. This paper extends our previous work on priority queuing and brings novelty in terms of presenting performance analysis of the converged ONU-BS under realistic traffic load conditions. Further, the presented analysis can be used as a network planning and optimization tool to select the most robust and appropriate queuing discipline for the ONU-BS relevant to the QoS requirements of different applications.

High Speed 8-Parallel Fft/ifft Processor using Efficient Pipeline Architecture and Scheduling Scheme (효율적인 파이프라인 구조와 스케줄링 기법을 적용한 고속 8-병렬 FFT/IFFT 프로세서)

  • Kim, Eun-Ji;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.3C
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    • pp.175-182
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    • 2011
  • This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.