• Journal of Korean Ophthalmic Optics Society
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• v.14 no.1
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• pp.63-68
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• 2009

Purpose: TiN films were deposited on sus304 by unbalanced magnetron sputtering system which was designed and developed as unbalancing the strength of the magnets in the magnetron electrode. The effect of oxygen incorporation in the fabrication of deposited films was investigated. Methods: The cross sections of deposited films on Silicon wafer were observed by SEM to measure the thickness of the films, the components of the surface of the films were identified by XPS survey spectra, the compositional depth-profile of deposited films was examined by an XPS apparatus. Results: From the data of XPS depth profile of films, it could be seen that the element O as well as the elements Ti and N present in the surface of the film and the relative percentage of the element O was constant at 65 at.% with respect to the depth of film. Conclusions: The color change with thickness of the films had something to do with the change of Ti $ 2p_{3/2}$ peak intensity and shape mixed of $ TiO_2$, TiN, $ TiO_{x}N_{y}$ compound.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.2
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• pp.103-108
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• 2019

Non-equilibrium molecular dynamics simulation on the thermal boundary resistance(TBR) of an aluminum(Al)/silicon(Si) interface was performed in the present study. The constant heat flux across the Si/Al interface was simulated by adding the kinetic energy in hot Si region and removing the same amount of the energy from the cold Al region. The TBR estimated from the sharp temperature drop at the interface was independent of heat flux and equal to $5.13{\pm}0.17K{\cdot}m^2/GW$ at 300K. The simulation result was experimentally confirmed by the time-domain thermoreflectance technique. A 90nm thick Al film was deposited on a Si(100) wafer using an e-beam evaporator and the TBR on the film/substrate interface was measured using the time-domain thermoreflectance technique based on a femtosecond laser system. A numerical solution of the transient heat conduction equation was obtained using the finite difference method to estimate the TBR value. Experimental results were compared to the prediction and discussions on the nanoscale thermal transport phenomena were made.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.9-15
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• 2021

Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (R_q) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

• Journal of Conservation Science
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• v.36 no.6
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• pp.511-518
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• 2020

There have been reports that the "jeongcho (定礎)" letters of the foundation stone at the historical site No. 280 of the "Main Building of the Bank of Korea in Seoul" were written by Prince Ito Hirobumi (伊藤博文), the first Resident-General of Japan in Korea. An on-site investigation by an advisory group consisting of three experts in calligraphy; revealed that the two characters of '定礎' inscribed on the foundation stone are the characteristics of Ito Hirobumi's handwriting, judging from the writing style and habits observed in the collections of the Central Library of Hamamatsu City, Japan. It was reported that his writing was confirmed by the experts, but no basis was provided. To provide more objective and quantitative supporting data, rather than qualitative judgment based on feeling, it is necessary to present the basis for judgment through quantitative image comparison results through image analysis. In this paper, using image analysis software, Ito Hirobumi's calligraphy writing and the inscribed characters of the foundation stone were compared and analyzed to confirm the contents of the press release. The character comparison process and character area measurement results are a good example showing that if objective judgment basis data are needed in a similar situation, an objective judgment basis can be prepared through quantification using image analysis.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.603-609
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• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.168-174
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• 1991

Ti-silicide was deposited by sputtering the composite target($TiSi_{2.6}$) on single-Si wafers and oxide on them. The heat treatment temperatures by rapid thermal annealing(RTA) have been varied in the range of $600-850^{\circ}C$ for 20seconds. It was not until RTA temperature was $800^{\circ}C$ that a stable $TiSi_2$ was formed, and the value of resistivity of that phase was $27~29{\mu}{\Omega}-cm$, which seems a little higher than that formed by the reactive method. The result of x-ray diffraction peals showed that till $750^{\circ}C$, C49 $TiSi_2$ phase was dominant, but at $800^{\circ}C$, at last, the phase was transformed into a stable C54 $TiSi_2$ phase. And, the result of x-ray photoeletron spectroscopy(XPS) measurements showed that the composition ratio of Ti and Si was 2 1 in the case of specimens treated at $800^{\circ}C$, The surface roughness of $TiSi_2$, which was condidered a weak point, was improved to a superior value of $17{\pm}1nm$, therefore increasing the possibility of applying $TiSi_2$ to semiconductor devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1281-1286
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• 2006

We have used the silicon-carbide(4H-SiC) instead of conventional silicon materials to develope of the planar junction barrier schottky rectifier for ultra high breakdown voltage(1,200 V grade). The substrate size is 2 inch wafer, Its concentration is $3*10^{18}/cm^{3}$ of $n^{+}-$type, thickness of epitaxial layer $12{\mu}m$ conentration is $5*10^{15}cm^{-3}$ of n-type. The fabticated devices are junction barrier schottky rectifier, The guard ring for improvement of breakdown voltage is designed by the box-like impurity of boron, the width and space of guard ring was designed by variation. The contact metals to rectify were used by the $Ni(3,000\:{\AA})/Au(2,000\:{\AA})$. As a results, the on-state voltage is 1.26 V, on-state resistance is $45m{\Omega}/cm^{3}$, maximum value of improved reverse breakdown voltage is 1180V, reverse leakage current density is $2.26*10^{-5}A/CM^{3}$. We had improved the measureme nt results of the electrical parameters.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.83-89
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• 2015

In this paper, we propose a fabrication technique for enhanced electrical properties of piezoelectric thick films with excellent patterning property using sol-infiltration and a direct-patterning process. To achieve the needs of high-density and direct-patterning at a low sintering temperature (< $850^{\circ}C$), a photosensitive lead zirconate titanate (PZT) solution was infiltrated into a screen-printed thick film. The direct-patterned PZT films were clearly formed on a locally screen-printed thick film, using a photomask and UV light. Because UV light is scattered in the screen-printed thick film of a porous powder-based structure, there are needs to optimize the photosensitive PZT sol infiltration process for obtaining the enhanced properties of PZT thick film. By optimizing the concentration of the photosensitive PZT sol, UV irradiation time, and solvent developing time, the hybrid films prepared with 0.35 M of PZT sol, 4 min of UV irradiation and 15 sec solvent developing time, showed a very dense with a large grain size at a low sintering temperature of $800^{\circ}C$. It also illustrated enhanced electrical properties (remnant polarization, $P_r$, and coercive field, $E_c$). The $P_r$ value was over four times higher than those of the screen-printed films. These films integrated on silicon wafer substrate could give a potential of applications in micro-sensors and -actuators.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.13-19
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• 2001

We report on the fabrication and characterization of $Al_{0.3}Ga_{0.7}N$ HFETs with different barrier layer thickness which were grown using plasma-assisted molecular beam epitaxy (PAMBE). The barrier thickness of $Al_{0.3}Ga_{0.7}N$/GaN HFETs could be optimized in order to maximize 2 dimensional electron gas induced by piezoelectric effect without the relaxation of $Al_{0.3}Ga_{0.7}N$ layer. $Al_{0.3}Ga_{0.7}N$/GaN (20 nm/2 mm) HFET with 0.6 ${\mu}m$-long and 34 ${\mu}m$-wide gate shows saturated current density ($V_{gs}=1\;V$) of 1.155 A/mm and transconductance of 250 ms/mm, respectively. From high frequency measurement, the fabricated $Al_{0.3}Ga_{0.7}N$/GaN HFETs showed $F_t=13$ GHz and $F_{max}=48$ GHz, respectively. The uniformity of less than 5% could be obtained over the 2 inch wafer. In addition to the optimization of epi-layer structure, the relation between breakdown voltage and high frequency characteristics has been examined.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.