• Journal of Sensor Science and Technology
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• v.1 no.1
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• pp.23-34
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• 1992

In order to fabricate magnetoresistive sensor, Fe-Ni and Co-Ni alleys were evaporated on the slide glass and the silicon wafers. Saturation magnetic induction($B_{s}$), coercive field strength($H_{c}$) and magnetoresistance were measured for fabricated samples. The evaporated Fe-Ni thin films show that the saturation magnetic induction was 0.65 T, and coercive field strength was 0.379 A/cm, and this value was changed to 0.370 A/cm(//), 0.390 A/cm(${\bot}$), respectively after magnetic annealing. For the measurement of coercive field strength, magnetizing frequency of 1 kHz was used. For the fabricated sensor element, the change of magnetoresistance (${\Delta}R/R$) was excessively unstable due to oxidation in the process of fabrication. The evaporated Co-Ni alloy thin films show that saturation magnetic induction was 0.66 T, and coercive field strengthes were 5.895 A/cm(//), 5.898 A/cm(${\bot}$), respectively, after magnetic annelaing. The change of magnetoresistance(${\Delta}R/R$) was $3.6{\sim}3.7%$ of which value was excessively stable to room temperature. Fe-Ni thin film could have many problems due to large affinity in the process of fabrication of magnetoresistance sensor, but Co-Ni thin film could be a suitable material for fabrication of magnetoresistance sensor, because of its small affinity and definite magnetoresistance effects.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.173-181
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• 1992

Tantalum pentoxide($Ta_{2}O_{5}$) thin films on p-type (100) silicon wafer were fabricated by RF reactive sputtering. Physical properties and structure of the specimens were examined by XRD and AES. From the C-V analysis, the dielectric constant of $Ta_{2}O_{5}$ films was in the range of 10-12 in the reactive gas atmosphere in which 10% of oxygen gas is mixed. The ratio of Ta : 0 was 1 : 2 and 1 : 2.49 by AES and RBS examination, respectively. The heat-treatment at $700^{\circ}C$ in $O_{2}$ ambient led to induce crystallization. When the heat-treatment temperature was $1000^{\circ}C$, the dielectric constant was 20.5 in $O_{2}$ ambient and 23 in $N_{2}$ ambient, respectively. The crystal structure of $Ta_{2}O_{5}$ film was pseudo hexagonal of ${\delta}-Ta_{2}O_{5}$. The flat band voltage shift(${\Delta}V_{FB}$) of the specimens and the leakage current density were decreased for higher oxygen mixing ratio. The maximum breakdown field was 2.4MV/cm at the oxygen mixing ratio of 10%. The $Ta_{2}O_{5}$ films will be applicable to hydrogen ion sensitive film and gate oxide material for memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.204-205
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• 2011

In thin film silicon solar cells, p-i-n structure is adopted instead of p/n junction structure as in wafer-based Si solar cells. PECVD is a most widely used thin film deposition process for a-Si:H or ${\mu}c$-Si:H solar cells. For best performance of thin film silicon solar cell, the dopant profiles at p/i and i/n interfaces need to be as sharp as possible. The sharpness of dopant profiles can easily achieved when using multi-chamber PECVD equipment, in which each layer is deposited in separate chamber. However, in a single-chamber PECVD system, doped and intrinsic layers are deposited in one plasma chamber, which inevitably impedes sharp dopant profiles at the interfaces due to the contamination from previous deposition process. The cross-contamination between layers is a serious drawback of a single-chamber PECVD system in spite of the advantage of lower initial investment cost for the equipment. In order to resolve the cross-contamination problem in single-chamber PECVD systems, flushing method of the chamber with NH3 gas or water vapor after doped layer deposition process has been used. In this study, a new plasma process to solve the cross-contamination problem in a single-chamber PECVD system was suggested. A single-chamber VHF-PECVD system was used for superstrate type p-i-n a-Si:H solar cell manufacturing on Asahi-type U FTO glass. A 80 MHz and 20 watts of pulsed RF power was applied to the parallel plate RF cathode at the frequency of 10 kHz and 80% duty ratio. A mixture gas of Ar, H2 and SiH4 was used for i-layer deposition and the deposition pressure was 0.4 Torr. For p and n layer deposition, B2H6 and PH3 was used as doping gas, respectively. The deposition temperature was $250^{\circ}C$ and the total p-i-n layer thickness was about $3500{\AA}$. In order to remove the deposited B inside of the vacuum chamber during p-layer deposition, a high pulsed RF power of about 80 W was applied right after p-layer deposition without SiH4 gas, which is followed by i-layer and n-layer deposition. Finally, Ag was deposited as top electrode. The best initial solar cell efficiency of 9.5 % for test cell area of 0.2 $cm^2$ could be achieved by applying the in-situ plasma cleaning method. The dependence on RF power and treatment time was investigated along with the SIMS analysis of the p-i interface for boron profiles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Journal of Sensor Science and Technology
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• v.6 no.5
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• pp.407-413
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• 1997

The crystallized CuPc(copper phthalocyanine) film on a p-type <100> Si substrate is prepared at the substrate temperature of $300^{\circ}C$ by thermal evaporation. X -ray diffraction analysis showed the CuPc film to have a-axis oriented structure. For the measurement of photovoltaic characteristics of the CuPc/Si film and the Si substrate, a transverse current-voltage (I-V) curve is observed. In the dark, the Au/Si junction is shown to be ohmic contact. However, under illumination, a photovoltaic effect is not observed. The I-V curve in the dark indicates that the CuPc film on Si may form an ohmic contact. Since the CuPc film is a p-type semiconductor, the CuPc/p-Si junction has no barrier at the interface. Under illumination, the CuPc/Si junction shows a large photocurrent comparing with that of the wafer. The result indicates that the CuPc layer plays an important role in the photocarrier generation under red illumination (600 nm). The CuPc/Si film shows the photo voltaic characteristics with a short-circuit photocurrent ($J_{sc}$) of $4.29\;mA/cm^{2}$ and an open-circuit voltage ($V_{oc}$) of 12 mA.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.173-173
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• 2010

Recently, a patterned sapphire substrate (PSS) has been intensively used as one of the effective ways to reduce the dislocation density for the III-nitride epitaxial layers aiming for the application of high-performance, especially high-brightness, light-emitting diodes (LEDs). In this paper, we analyze the growth kinetics of the atoms and crystalline quality for the undopped-GaN depending on the facets of the pattern fabricated on a sapphire substrate. The effects of the PSS on the device characteristics of InGaN/GaN LEDs were also investigated. Several GaN samples were grown on the PSS under the different growth conditions. And the undoped-GaN layer was grown on a planar sapphire substrate as a reference. For the (002) plane of the undoped-GaN layer, as an example, the line-width broadening of the x-ray diffraction (XRD) spectrum on a planar sapphire substrate is 216.0 arcsec which is significantly narrower than that of 277.2 arcsec for the PSS. However, the line-width broadening for the (102) plane on the planar sapphire substrate (363.6 arcsec) is larger than that for the PSS (309.6 arcsec). Even though the growth parameters such as growth temperature, growth time, and pressure were systematically changed, this kind of trend in the line-width broadening of XRD spectrum was similar. The emission wavelength of the undoped-GaN layer on the PSS was red-shifted by 5.7 nm from that of the conventional LEDs (364.1 nm) under the same growth conditions. In addition, the intensity for the GaN layer on the PSS was three times larger than that of the planar case. The spatial variation in the emission wavelength of the undoped-GaN layer on the PSS was statistically ${\pm}0.5\;nm$ obtained from the photoluminescence mapping results throughout the whole wafer. These results will be discussed in terms of the mixed dislocation depending on the facets and the period of the patterns.

• Journal of IKEEE
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• v.22 no.4
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• pp.1226-1229
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• 2018

We investigated the improvement of surface roughness and states after high temperature annealing using reduced-graphene oxide (r-GO) capping layer on ion-implanted 4H-SiC epitaxial layer. The specification of the 4H-SiC wafer grown on n-type $4^{\circ}$ off-axis 4H-SiC was $10{\mu}m$-thick and n-type epitaxial layer with a dose of $1.73{\times}10^{15}cm^{-2}$. The $n^+$ region were formed by multiple nitrogen ion-implantations and r-GO capping layer was produced by spray coating method. AFM measurements revealed that RMS value of the sample capped with r-GO was tenfold decrease compared to the sample without r-GO capping. The improvement of surface states was also verified by the improvement of leakage current level.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.2
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• pp.103-108
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• 2019

Non-equilibrium molecular dynamics simulation on the thermal boundary resistance(TBR) of an aluminum(Al)/silicon(Si) interface was performed in the present study. The constant heat flux across the Si/Al interface was simulated by adding the kinetic energy in hot Si region and removing the same amount of the energy from the cold Al region. The TBR estimated from the sharp temperature drop at the interface was independent of heat flux and equal to $5.13{\pm}0.17K{\cdot}m^2/GW$ at 300K. The simulation result was experimentally confirmed by the time-domain thermoreflectance technique. A 90nm thick Al film was deposited on a Si(100) wafer using an e-beam evaporator and the TBR on the film/substrate interface was measured using the time-domain thermoreflectance technique based on a femtosecond laser system. A numerical solution of the transient heat conduction equation was obtained using the finite difference method to estimate the TBR value. Experimental results were compared to the prediction and discussions on the nanoscale thermal transport phenomena were made.

• Clean Technology
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• v.16 no.3
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• pp.191-197
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• 2010

Repair reaction of plasma damaged porous methyl doped SiOCH films was carried out with silylation agents dissolved in supercritical carbon dioxide ($scCO_2$) at various reaction time, pressure, and temperature. While a decrease in the characteristic bands at $3150{\sim}3560cm^{-1}$ was detectable, the difference of methyl peaks was not identified apparently in the FT-IR spectra. The surface hydrophobicity was rapidly recovered by the silylation. In order to induce effective repair in bulk phase, the wafer was heat treated before reaction under vacuum or ambient condition. The contact angle was slightly increased after the treatment and completely recovered after the subsequent silylation. Methyl groups were decreased after the plasma damage, but their recovery was not identified apparently from the FT-IR, spectroscopic ellipsometry, and secondary ion mass spectroscopy analyses. Furthermore, Ti evaporator was performed in a vacuum chamber to evaluate the pore sealing effect. The GDS analysis revealed that the open pores in the plasma damaged films were efficiently sealed with the silylation in $scCO_2$.