• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.59-65
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• 1999

In this paper, we had studied the possibility of application as Cu thin films from (hfac)Cu(VTMOS) which is very stable. Cu thin films had been studied as a function of deposition temperature. Substrates used in the experiment were PVD TiN on Si wafer. Deposition conditions were as follow : deposition temperature $50^{\circ}C$. Cu thin films were analyzed by AES, four point probe, XRD and SEM. All of deposited films were very pure and some favoring of <111> planes perpendicular to the substrate surface were observed. Cu thin films had two distinct growth rates at various deposition temperature. One is the surface reaction limited region below $200^{\circ}C$, and the other is the mass transport limited region above $200^{\circ}C$. The resistivity of deposited Cu thin films under the optimum deposition condition is $2.5mu\Omega.cm$ Thus, properties of deposited Cu thin films using (hfac)Cu(VTMOS) didn't show difference with Cu thin films from other precursors.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.34 no.1
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• pp.73-76
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• 2010

The issue of inspection and characterization of microstructures has emerged as a major consideration in design, fabrication, and detection of MEMS devices. However, the conventional measurement techniques, including scanning electron microscopy (SEM) imaging, atomic force microscopy (AFM) scanning, and mechanical surface profiler, require often destructive process or may be difficult to measure with a wafer scale. In this paper, we characterize the surface profiles of microstructures using an optical scanner based on a DVD pick-up module. Scanning images of the microstructures are successfully generated using the intensity of reflected light from different depths of the surface profiles, based on the focus error signal (FES) from photodiodes. It is shown that the proposed optical scanner can be used as an alternative measurement system with high performance and low cost, compared to conventional measurement techniques.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.40-45
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• 1994

$112^{\circ}$ rot. x-cut $LiTaO_{3}$ wafer was used as the substrate of SAW gas sensor. Dual delay line SAW device with IDTs which consist of the reference delay line and the sensing delay line was fabricated using photolithigraphy. Each IDTs had 10 finger pairs and finger spacing is 10 microns. One delay line channel is the reference, while the second is the sensing channel with Pb-phthalocyanine film in the propagation path. Pb-phthalocyanine film which is p-type organic semiconductor was evaporated in $10^{-5}$ torr vacuum using shadow mask selectively. Dual delay line oscillator was constructed by using the rf amplifier and AGC. Frequency of the IDTs had the range of $87{\sim}$89 MHz oscillation frequency. Oscillation frequency shifts were investigated as a function of the temperature and the concentration of $NO_{2}$ gas.

• Korean Journal of Materials Research
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• v.22 no.9
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• pp.450-453
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• 2012

In crystalline solar cells, the substrate itself constitutes a large portion of the fabrication cost as it is derived from semiconductor ingots grown in costly high temperature processes. Thinner wafer substrates allow some cost saving as more wafers can be sliced from a given ingot, although technological limitations in slicing or sawing of wafers off an ingot, as well as the physical strength of the sliced wafers, put a lower limit on the substrate thickness. Complementary to these economical and techno-physical points of view, a device operation point of view of the substrate thickness would be useful. With this in mind, BC-BJ Si and GaAs solar cells are compared one to one by means of the Medici device simulation, with a particular emphasis on the substrate thickness. Under ideal conditions of 0.6 ${\mu}m$ photons entering the 10 ${\mu}m$-wide BC-BJ solar cells at the normal incident angle (${\theta}=90^{\circ}$), GaAs is about 2.3 times more efficient than Si in terms of peak cell power output: 42.3 $mW{\cdot}cm^{-2}$ vs. 18.2 $mW{\cdot}cm^{-2}$. This strong performance of GaAs, though only under ideal conditions, gives a strong indication that this material could stand competitively against Si, despite its known high material and process costs. Within the limitation of the minority carrier recombination lifetime value of $5{\times}10^{-5}$ sec used in the device simulation, the solar cell power is known to be only weakly dependent on the substrate thickness, particularly under about 100 ${\mu}m$, for both Si and GaAs. Though the optimum substrate thickness is about 100 ${\mu}m$ or less, the reduction in the power output is less than 10% from the peak values even when the substrate thickness is increased to 190 ${\mu}m$. Thus, for crystalline Si and GaAs with a relatively long recombination lifetime, extra efforts to be spent on thinning the substrate should be weighed against the expected actual gain in the solar cell output power.

• Journal of the Korean Vacuum Society
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• v.16 no.2
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• pp.110-115
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• 2007

A plasma enhanced atomic layer deposition(PEALD) system has been constructed adopting an inductively coupled plasma(ICP) source with an ALD system, and its plasma generation was carried out. Cobalt thin films were deposited on a p-type Si(100) wafer at $230^{\circ}C$. $Co_{2}(CO)_{6}$ was used as a cobalt precursor, $NH_{3}$ as a reactant, and Ar as a carrier and purge gas. The properties of the thin films were investigated using field emission scanning electron microscopy(FESEM) and auger electron spectroscopy(AES). Large amounts of impurities were found in both the ALD film and the PEALD film, however, the amount of impurities in the PEALD film was reduced to about 50 % compared to that in the ALD film. It was found that $NH_{3}$ plasma, very effectively, induces the reaction with carbon in a cobalt precursor.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.756-759
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• 2004

We present a piezoelectric actuator using stiffness control and stroke amplification mechanism in order to make large lateral displacement. In this work, we suggest stiffness control approach that generates lateral displacement by increasing the vertical stiffness and reducing the lateral stiffness using additional structure. In addition, an additional structure of a serpentine spring amplifies the lateral displacement like leverage structure. The suggested lateral PZT actuator (bellows actuator) consists of serpentine spring and PZT/electrode layer which is located at the edge of the serpentine spring. The edge of the serpentine spring prevents the vertical motion of PZT layer, while the other edge of the serpentine spring makes stroke amplification like leverage structure. We have determined dimensions of the bellows actuator using ANSYS simulation. Length, width and thickness of PZT layer are 135$\mu$m, 20$\mu$m and 0.4$\mu$m, respectively. Dimensions of the silicon serpentine spring are thickness of 25$\mu$m, length of 300$\mu$m, and width of 5$\mu$m. The bellows actuator has been fabricated by SOI wafer with 25$\mu$m-top silicon and 1$\mu$m-buried oxide layer. The bellows actuator shows the maximum 3.93$\pm$0.2$\mu$m lateral displacement at 16V with 1Hz sinusoidal voltage input. In the frequency response test, the fabricated bellows actuator showed consistent displacement from 1Hz to 1kHz at 10V. From experimental study, we found the bellows actuator using thin film PZT and silicon serpentine spring generated mainly laterally displacement not vertical displacement at 16V, and serpentine spring played role of stroke amplification.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.89-89
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• 2009

높은 소수반송자 수명(life-time)을 가지는 고품위 실리콘 기판은 고효율 실리콘 이종접합 태양전지 제작을 위한 중요 요소 기술 중 하나이다. 본 연구에서는 n-type c-Si 기판을 이용한 고효율 실리콘 이종접합 태양전지제작을 위해 hot water oxidation(HWO) 공정을 이용하여 고품위 실리콘 기판을 제작하였다. 실리콘 기판의 특성 분석은 Qusi-steady state photoconductance (QSSPC)를 이용하여 소수반송자 수명을 측정하였으며, 기판의 면저항 및 wetting angle을 측정하여 공정에 따른 특성변화를 분석하였다. Saw damage etching 된 기판을 웨이퍼 표면으로부터 particle, 금속 불순물, 유기물 등의 오염을 제거하기 위해 $60{\sim}85^{\circ}C$로 가열된 Ammonia수, 과산화수소수($NH_4OH/H_2O_2/H_2O$), 염산 과산화수소수($HCL/H_2O_2/H_2O$) 및 실온 희석불산(DHF) 중에 기판을 각각 10분 정도씩 침적하여, 각각의 약액 처리 후에 매회 10분 정도씩 순수(DI water)에서 rinse하여 RCA 세정을 진행한 후 HWO 공정을 통해 기판 표면에 얇은 산화막 을 형성시켜 패시베이션 해주었다. HF를 이용하여 자연산화막을 제거시 HWO 공정을 거친 기판은 매끄러운 표면과 패시베이션 영향으로 기판의 소수 반송자 수명이 증가하며, 태양전지 제작시 접촉저항을 감소시켜 효율을 증가 시킬수 있다. HWO 공정은 반응조 안의 DI water 온도와 반응 시간에 따라 life-time을 측정하여 진행하였으며, 이후 PE-CVD법으로 증착된 a-Si:H layer 및 투명전도 산화막, 금속전극을 증착하여 실리콘 이종접합 태양전지를 제작하였다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.107.1-107.1
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• 2011

현재 상용으로 많이 사용되는 p-type 태양전지는 Dopant로 사용된 Boron이 $O_2$와 결합하면서 Light induced degradation이 발생하여 태양 전지 효율의 감소를 불러일으키는 단점이 있다. 이러한 문제를 해결하기 위하여 여러 가지 방법들이 제시되었는데 일반적으로 n-type wafer를 이용함으로써 Light induced degradation을 해결하는 방법이 주로 사용된다. n-type 태양전지를 제조함에 있어서 보다 높은 효율을 달성하기 위하여 태양전지 후면 구조에 local contact 개념을 도입하여 rear local emitter를 형성함으로써 전체적인 효율 증가를 도모하였다. 이러한 local contact을 제조하기 위해서는 전기적으로 구조적으로 고려할 사항들이 여러 가지 존재한다. 따라서 우리는 이러한 고려 사항들을 실험적인 방법으로 결정하는 것이 아니라, 정교한 변수 통제를 이용한 시뮬레이션으로 최종적인 효율 상승을 가져오는 조건을 찾으려고 한다. 이때 사용될 수 있는 시뮬레이션은 여러 가지 종류가 존재하는데 우선 상용 태양전지의 해석에 가장 많이 사용되는 PC1D프로그램이 있다. 그러나 PC1D의 경우에는 1차원의 해석만 가능하기 때문에 local contact의 2차원 이상의 구조 변화에 따른 최종적인 효율을 계산하는데 무리가 따르게 된다. 따라서 2차원 이상의 형상에 대한 분석이 가능한 프로그램을 이용하여 실제 셀에서 일어나는 현상을 더 정밀하게 모사함으로써 local contact에서 일어나는 전기적, 구조적 변화가 최종적인 효율에 어떻게 영향을 미치는지를 파악해볼 것이며, 어떤 구조를 선택하였을 때 가장 높은 효율을 달성할 수 있는지 알아보려고 한다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.34.2-34.2
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• 2011

The demand for Ru has been increasing in the electronic, chemical and semiconductor industry. Chemical mechanical planarization (CMP) is one of the fabrication processes for electrode formation and barrier layer removal. The abrasive particles can be easily contaminated on the top surface during the CMP process. This can induce adverse effects on subsequent patterning and film deposition processes. In this study, a post Ru CMP cleaning solution was formulated by using sodium periodate as an etchant and citric acid to modify the zeta potential of alumina particles and Ru surfaces. Ru film (150 nm thickness) was deposited on tetraethylorthosilicate (TEOS) films by the atomic layer deposition method. Ru wafers were cut into $2.0{\times}2.0$ cm pieces for the surface analysis and used for estimating PRE. A laser zeta potential analyzer (LEZA-600, Otsuka Electronics Co., Japan) was used to obtain the zeta potentials of alumina particles and the Ru surface. A contact angle analyzer (Phoenix 300, SEO, Korea) was used to measure the contact angle of the Ru surface. The adhesion force between an alumina particle and Ru wafer surface was measured by an atomic force microscope (AFM, XE-100, Park Systems, Korea). In a solution with citric acid, the zeta potential of the alumina surface was changed to a negative value due to the adsorption of negative citrate ions. However, the hydrous Ru oxide, which has positive surface charge, could be formed on Ru surface in citric acid solution at pH 6 and 8. At pH 6 and 8, relatively low particle removal efficiency was observed in citric acid solution due to the attractive force between the Ru surface and particles. At pH 10, the lowest adhesion force and highest cleaning efficiency were measured due to the repulsive force between the contaminated alumina particle and the Ru surface. The highest PRE was achieved in citric acid solution with NaIO4 below 0.01 M at pH 10.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.1
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• pp.33-40
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• 1992

Several etching phenomena were observed and analyzed in diaphragm process performed on 4-inch (100) Si wafers for sensor application. In case of deep etching to above 300$\mu$m depth, the etch-defects appeared at etched surface could be classified into three categories such as hillocks, reaction products, and white residues. It was known that the hillock had a pyramidal shape or trapizoidal hexahedron structure depending on the density and size of the reaction products. The IR spectra showed that the white residue, which was due to the local over-saturation of Si dissolved in solution, was mostly Si-N-O compounds mixed with a small amount of H and C etc. Also, the difference in both the existence of etch-defects and etch rate distribution over a whole wafer was investigated when the etched surfaces were downward, upward horizontally and erective in etching solutions. The obtained data were analyzed through flow pattern in the etching bath. As the results, the downward and erective postures were favorable in the etch rate uniformity and the etch-defect removal, respectively.