• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1600-1604
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.389-392
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and non-uniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between particle size and CMP with particle size analysis of used slurry.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.441-442
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• 2002

Chemical mechanical polishing (CMP) is a manufacturing process that uses controlled wear to planarize dielectric and metallic layers on silicon wafers. CMP experiments revealed that a sub-ambient film pressure developed at the wafer/pad interface. Additionally, dishing occurs in CMP processes when the copper-in-trench lines are removed at a rate higher than the barrier layer. In order to study dishing across a stationary wafer during polishing, dishing maps were created. Since dishing is a function of the total contact pressure resulting from the applied load and the fluid pressure, the hydrodynamic pressure model was refined and used in an existing model to study copper dishing. Density maps, highlighting varying levels of dishing across the wafer face at different radial positions, were developed. This work will present the results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.88-91
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• 2003

Tungsten is widely used as a plug for the multi-level interconnection structures. However, due to the poor adhesive properties of tungsten (W) on $SiO_2$ layer, the Ti/TiN barrier layer is usually deposited onto $SiO_2$ for increasing adhesion ability with W film. Generally, for the W-CMP (chemical mechanical polishing) process, the passivation layer on the tungsten surface during CMP plays an important role. In this paper, the effect of oxidants controlling the polishing selectivity of W/Ti/TiN layer were investigated. The alumina ($Al_2O_3$) abrasive containing slurry with $H_2O_2$ as the oxidizer, was studied. As our preliminary experimental results, very low removal rates were observed for the case of no-oxidant slurry. This low removal rate is only due to the mechanical abrasive force. However, for Ti and TiN with $H_2O_2$ oxidizer, different removal rate was observed. The removal mechanism of Ti during CMP is mainly due to mechanical abrasive, whereas for TiN, it is due to the formation of metastable soluble peroxide complex.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.140-143
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• 2003

BST thin films have a good thermal-chemical stability, insulating effect and variety of phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.33-36
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• 2003

Tungsten is widely used as a plug for the multi-level interconnection structures. However, due to the poor adhesive properties of tungsten (W) on $SiO_2$ layer, the Ti/TiN barrier layer is usually deposited onto $SiO_2$ for increasing adhesion ability with W film. Generally, for the W-CMP (chemical mechanical polishing) process, the passivation layer on the tungsten surface during CMP plays an important role. In this paper, the effect of oxidants controlling the polishing selectivity of W/Ti/TiN layer were investigated. The alumina $(Al_2O_3)$ abrasive containing slurry with 5 % $H_2O_2$ as the oxidizer, was studied. As our preliminary experimental results, very low removal rates were observed for the case of no-oxidant slurry. This low removal rate is only due to the mechanical abrasive force. However, for Ti and TiN with 5 % $H_2O_2$ oxidizer, different removal rate was observed. The removal mechanism of Ti during CMP is mainly due to mechanical abrasive, whereas for TiN, it is due to the formation of metastable soluble peroxide complex.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.434-437
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• 2005

Chemical Mechanical Polishing (CMP) has become an essential step in the overall semiconductor wafer fabrication technology. In general, CMP is a surface planarization method in which a silicon wafer is rotated against a polishing pad in the presence of slurry under pressure. The polishing pad, generally a polyurethane-based material, consists of polymeric foam cell walls, which aid in removal of the reaction products at the wafer interface. It has been found that the material removal rate of any polishing pad decreases due to the so-called 'pad glazing' after several wafer lots have been processed. Therefore, the pad restoration and conditioning has become essential in CMP processes to keep the urethane polishing pad at the proper friction coefficient and to allow effective slurry transport to the wafer surface. Diamond pad conditioner employs a single layer of brazed bonded diamond crystals. Due to the corrosive nature of the polishing slurry required in low pH metal CMP such as copper, it is essential to minimize the possibility of chemical interaction between very low pH slurry (pH <2) and the bond alloy. In this paper, we report an exceptional protective coated conditioner for in-situ pad conditioning in low pH Cu CMP process. The protective Cr-coated conditioner has been tested in slurry with pH levels as low as 1.5 without bond degradation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.35-36
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• 2012

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.439-440
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• 2002

Nano-Crystalline $CeO_2$ particles were dispersed in deionized water with controlled slurry chemicals for CMP test. According to the CMP test, the removal rate of $SiO_2$ layer was mainly controlled by the size and crystallinity of $CeO_2$ particles which can be controlled by the heat-treatment condition during $CeO_2$ synthesis. In contrast, the removal rate of $Si_3N_4$ layer was significantly influenced by the passivation reagent which protects the $Si_3N_4$ surface layer from excessive dissolution during CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.715-718
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• 2004

In this paper, we studied the characteristics of new polishing pad, which can apply W-CMP process for global planarization of multi-level interconnection structure. The hardness and density were measured as a function of groove pattern. Also, we compared the pore size through the SEM photograph. Finally, we investigated the CMP characteristics with five different kind of groove pattern sample. Through the above results, we can select optimum groove pattern, so we can expect to begin home product of polishing pad.