• 전자공학회논문지S
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• 제35S권3호
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• pp.19-28
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• 1998

This paper is concerned with the implementation of the equalization technique in a DCS 1800 system employing the soft-decision output Viterbi algorithm (SOVA), which makes the hardware complexity comparable to the hard decision MLSE and gives reliable performance. Also, the channel estimation technique with enhances the perfdormance of the soft-decision output equalizer is proposed, and the Viterbi decoder which operates effectively with the soft-decision output of the qualizer is implemented using the Very High Speed ICs Hardware Description Language (VHDL). From the simulation results, it is shown that the implemented Viterbi decoder operates effectively and the SOVA outperforms the hard-decision MLSE in terms of the frame erasure rate (FER) and bit error rate (BER).

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• 한국통신학회논문지
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• 제21권8호
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• 한국통신학회논문지
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• 제27권1C호
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• pp.84-89
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• 2002

제출된 논문에서는 고음질의 오디오 신호를 전송하는 무선 모뎀의 수신부에서 TCM 복호와에 사용되는 Viterbi 디코더를 VHDL을 이용하여 설계하고 FPGA를 이용하여 구현하였다. 이 논문에서는 TCM 부호화와 복호화와 복호화 과정을 간단히 설명한 후 부호화기와 복호화기를 FPGA로 구현한 다음 PC 상에서 채널의 영향을 재현하여 신호 대잡음비($E_b/N_0$) 변화에 따른 시스템의 비트에러율 성능을 제시하고 있다.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
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• pp.217-221
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• 2003

In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-OFDM. The proposed Viterbi decoder is conceptually same as the multiple Phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency. Also, the proposed algorithm can be used in the single carrier modulation.

• 한국통신학회논문지
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• 제21권2호
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• pp.483-494
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• 1996

In this paper, we proposed the receive decoder and Virterbi algorithm with sliding multiple symbol detection using MLSE. the informationis transmitted by the phase difference of the adjacent channel signal at the .pi./4 shift QPSK. In order to apply the .pi./4 shift QPSK to TCM, we use the signal set expansion and the signal set partition by the phase differences. And the Viterbi decoder containing branch mertrice of the squared Euclidean distance of the first, second and Lth order phase difference is introduced in order to extract the information in the differential detection of the Trellis-Coded .pi./4 shift QPSK. The proposed Viterbi decoder and receiver are conceptually same to the sliding multiple symbol detection method using the MLSE. By uisng this method, the study shows that the Trellis-Coded .pi./4 shift QPSK is an attractive scheme for the power and the bandimited systems while also improving the BER performance when the Viterbi decoder is employed to the Lth order phase difference metrics.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3199-3201
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• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

• ETRI Journal
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• 제30권6호
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• pp.850-852
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• 2008

This letter presents a power efficient 64-state Viterbi decoder (VD) employing a two-stage radix-4 add-compare-select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared. Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency-division multiplexing (MB-OFDM) ultra-wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18-${\mu}m$ CMOS technology.

• 대한전자공학회논문지TC
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• 제42권5호
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• pp.13-22
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• 2005

OFDM(orthogonal frequency division multiplexing) 변조를 이용한 WLAN(wireless local area network) 시스템은 고속 무선 데이터 통신을 위한 대표적 수단으로 전송률의 향상을 위해 활발히 연구되고 있다. 본 논문에서는 WLAN의 정확한 채널 등화와 샘플링 클럭 추적을 위하여 비터비 복호기 출력을 이용한 등화 및 샘플링 클럭 추적 알고리듬을 제안한다. 이 알고리듬은 파일럿 신호를 이용하여 대략의 클럭 주파수 복원과 채널등화를 수행한 후 비터비 복호기의 출력을 다시 부호화하여 등화 및 샘플링 클럭의 추적에 이용하는 알고리듬이다. 제안한 알고리듬의 우수성을 ETSI WLAN 채널 환경에서 컴퓨터 모의실험을 통하여 보였다.

• 한국통신학회논문지
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• 제19권4호
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• pp.712-720
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• 1994

디지털 이동 통신 시스템에서, 길쌈부호는 최적 에러정정기법이라 생각된다. 최근 디지털 이동 통신의 부호정정을 위하여 Viterbi 알고리즘은 길쌈부호의 부호화를 위해 가장 널리 사용된다. Viterbi 디코더의 하드웨어 설계를 위하 많은 방법들이 대부분 부호기의 부호율 R=1/2 또는 2/3인 메모리 소자수가 적고 부호 구속장이 짧은 것으로 제안되었다. 본 논문에서는, 지연 메모리 기억소자인 m=6의 부호율 R=1/2 K=1/2, K=7(171,133) 길쌈부호기를 위한 설계방식을 고려하였다. Viterbi 알고리즘에 상태천이 이중검색 방식을 이용한 새로운 기법을 제안하였다. 그리고 회로설계는 랜덤 2비트 에러 정정 복원할 수 있도록 하였다. 시뮬레이션 결과, 제안된 Viterbi 디코더는 1비트와 2비트 에러신호에 대하여 정확하게 정정하였다.