• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.3
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• pp.19-28
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• 1998

This paper is concerned with the implementation of the equalization technique in a DCS 1800 system employing the soft-decision output Viterbi algorithm (SOVA), which makes the hardware complexity comparable to the hard decision MLSE and gives reliable performance. Also, the channel estimation technique with enhances the perfdormance of the soft-decision output equalizer is proposed, and the Viterbi decoder which operates effectively with the soft-decision output of the qualizer is implemented using the Very High Speed ICs Hardware Description Language (VHDL). From the simulation results, it is shown that the implemented Viterbi decoder operates effectively and the SOVA outperforms the hard-decision MLSE in terms of the frame erasure rate (FER) and bit error rate (BER).

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.84-89
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• 2002

In this paper the Viterbi decoder which is used for TCM decoding in wireless modem system under transmission of audio data for the high quality sound is designed by VHDL and implemented by FPGA. After making short explanation about TCM encoding and decoding. I show the effect of channel in computer by using encoder and decoder implemented in FOGA and the bit error rate according to change rate of ($E_b/N_0$).

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.217-221
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• 2003

In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-OFDM. The proposed Viterbi decoder is conceptually same as the multiple Phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency. Also, the proposed algorithm can be used in the single carrier modulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.483-494
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• 1996

In this paper, we proposed the receive decoder and Virterbi algorithm with sliding multiple symbol detection using MLSE. the informationis transmitted by the phase difference of the adjacent channel signal at the .pi./4 shift QPSK. In order to apply the .pi./4 shift QPSK to TCM, we use the signal set expansion and the signal set partition by the phase differences. And the Viterbi decoder containing branch mertrice of the squared Euclidean distance of the first, second and Lth order phase difference is introduced in order to extract the information in the differential detection of the Trellis-Coded .pi./4 shift QPSK. The proposed Viterbi decoder and receiver are conceptually same to the sliding multiple symbol detection method using the MLSE. By uisng this method, the study shows that the Trellis-Coded .pi./4 shift QPSK is an attractive scheme for the power and the bandimited systems while also improving the BER performance when the Viterbi decoder is employed to the Lth order phase difference metrics.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3199-3201
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• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

• ETRI Journal
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• v.30 no.6
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• pp.850-852
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• 2008

This letter presents a power efficient 64-state Viterbi decoder (VD) employing a two-stage radix-4 add-compare-select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared. Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency-division multiplexing (MB-OFDM) ultra-wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18-${\mu}m$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.13-22
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• 2005

IEEE 802.11a is a standard for the high-speed wireless local area network (WLAN), supporting from 6 up to 54 Mbps in a 5 GHz band. We propose a channel equalization algerian and a sampling clock recovery algorithm by utilizing the Viterbi decoder output of the IEEE 802.11a WLAN standard. The proposed channel equalizer adaptively compensates channel variations. The proposed system uses re-encoded Viterbi decoder outputs as reference symbols for the adaptation of the channel equalizer. It also extracts sampling phase information with the Viterbi decoder outputs for fine adjustment of the sampling clock. The proposed sampling clock recovery and equalizer are more robust to noise and frequency selective fading environments than conventional systems using only four pilot samples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.712-720
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• 1994

In digital mobile communication systems, the convolutional coding is considered as the optimum error correcting scheme. Recently, the Viterbi algorithm is widely used for the decoding of convolutional code. Most Viterbi decoder has been proposed in conde rate R=1/2 or 2/3 with memory components (m) less than 3. which degrades the error correcting capability because of small code constraints (K). We consider the design method for typical code rate R=1/2, K=7(171,133) convolutional code with memory components, m=6. In this paper, a novel construction method is presented which combines maximum likelihood decoding with a state transition double detection and comparison method. And the designed circuit has the error-correcting capability of random 2 bit error. As the results of logic simulation, it is shown that the proposed Viterbi decoder exactly corrects 1 bit and 2 bit error signal.