• Journal of IKEEE
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• v.27 no.4
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• pp.494-500
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• 2023

Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.