• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.281-284
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• 2002

Error resilience for image coding is an important component of multimedia communication system. Error resilience schemes address loss recovery from the compression perspective. Multiple description coding (MDC) is one of the error resilience techniques promising for robust video transmission. It is the way to achieve tradeoff description such as scalar quantization, correlating transform and the quantized frame expansion. In this paper, we consider Multiple Description Scalar Quantization (MDSQ) to wavelet domain. Conventional MDSQ schemes considered description with equal weights in each sub-bands. But, we can see that the each sub-bands is unequal contribution to whole image quality. Therefore, we experiment the multiple design MDSQ table to make probability of zero index high, which gives high efficiency in arithmetic symbol coder. We also compare our proposed method with the conventional methods and show improved performance in terms of redundancy-rate-distortion.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.7
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• pp.332-338
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• 2001

A visually adaptive quantization method of DCT-based images based on Human Visual System(HVS) is proposed. This approach uses the spatial masking in HVS characteristics to obtain higher compression ratio with relatively small degradation in the image quality. HVS is nonsensitive to an edge area, so a high complexity area is quantized coarsely in contrast to fine quantization of the low complexity area. The complexity of an area is estimated by the variance of DCT coefficients of the image. Experimental results demonstrate the performance of the proposed method and the resulting images show little difference from the original image in the subjective perception.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.20-28
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• 1997

In this paper, quantization and inverse quantizatio unit, a sa component of MPEG-2 moving picture compression system, ar edesigned. In the processing of quantization, this design adopted newly designed arithmetic units in which quantization matrices and scale code was expressed with SD(signed-digit) code. In the arithmetic unit of inverse quantization, quantization scale code, which has 5-bits length, is splited into two pieces; 2-bits for control code, 3-bits for quantization data, and the method to devise quantization step size is proposed. The design was coded with VHDL and synthesis results in that it consumed about 6,110 gates, and operating speed is 52MHz.

• Proceedings of the Korea Contents Association Conference
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• 2010.05a
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• pp.437-440
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• 2010

동영상, 음악, 카메라영상, 음성 등 다양한 객체를 결합하는 강의 제작기는 강의 콘텐츠 제작에 유용하다. 본 프로그램은 다양한 객체를 결합하여 무 손실 압축 처리한 강의 콘텐츠를 제작한다. 결과물로서 음성/영상/인덱스의 3가지 종류의 파일이 생성된다. 인덱스파일은 영상 정보, 영상 파일 구성정보, 음성정보, 음성파일 구성정보를 가지며 음성파일은 각 객체의 음성만을 interpolation 처리 후 하나의 데이터로서 혼합한 결과물이다. 영상 파일은 영상 정보만을 결합한 뒤 wavelet, motion estimation, 사전코드 방식과 huffmancode 방식을 혼합한 방식을 응용한 무 손실 압축 영상데이터 이다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.130-139
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• 1994

Video compression algorithms are based on removing spatial and/or temproal redundancy inherent in image sequences by predictive(DPCM) encoding, transform encoding, or a combination of predictive and transform encoding. In this paper, each 8$\times$8 DCT coefficient of DFD(displaced frame difference) is adaptively quantized by one of the four quantizers depending on total distortion level, which is determined by characteristics of HVS(human visual system) and buffer status. Therefore, the number of possible quantizer selection vectors(patterns) is 4$^{64}$. If this vectors are coded, toomany bits are required. Thus, the quantizer selection vectors are limited to 2048 for Y and 512 for each U, V by the proposed method using SWAD(sum of weighted absolute difference) for discriminating vectors. The computer simulation results, using the codebook vectors which are made by the proposed method, show that the subjective and objective image quality (PSNR) are goor with the limited bit allocation. (17Mbps)

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.38-40
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• 2007

In this paper, we propose a novel architecture, which is based on DCT (Discrete Cosine Transform), for ME (Motion Estimation) and MC (Motion Compensation). The traditional algorithms of ME and MC based on DCT did not suffer the advantage of the coarseness of the 2-dimensional DCT (2-D DCT) coefficients to reduce the operational time. Therefore, we derive a recursion equation for transform-domain ME and MC and design the structure by using highly regular, parallel, and pipeline processing elements. The main difference with others is removing the IDCT block by using to transform domain. Therefore, the performance of our algorithm is more efficient in practical image processing such as DVR (Digital Video Recorder) system. We present the simulation result which is compare with the spatial domain methods. it shows reducing the calculation cost. compression ratio. and peak signal to noise ratio (PSNR).

• Transactions on Electrical and Electronic Materials
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• v.13 no.6
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• pp.278-282
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• 2012

Photovoltaic systems have emerged to be one of the cleanest energy systems. Therefore, many large scale solar parks and PV farms have been built to prepare for the post fossil fuel ages. However, due to their large scale, to efficiently manage and operate PV systems, they need to be visually monitored within the range of infrared ray through the Internet. To satisfy this need, the efficient implementation of a high performance video compression standard is required. This paper therefore presents an implementation of H.264 motion estimation, which is one of the most data-intensive and complicated functions in H.264. To achieve this, this work implements vector instructions in hardware and incorporates them in a generic RISC processor architecture, thus increasing the processing speed while minimizing hardware and software design efforts. Extensive simulation results show that this proposed implementation can process motion estimations up to 13 times faster.

• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.298-306
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• 2013

The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.