• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.252-255
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• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• Journal of Electrochemical Science and Technology
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• v.11 no.1
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• pp.60-67
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• 2020

In this study, copper (II) oxide powder for electroplating was prepared by recovering CuCl₂ from NaClO₃ type etching wastes via recovered non-sintering two step chemical reaction. In case of alkali copper carbonate [mCuCo₃·nCu(OH)₂], first reaction product, CuCo₃ is produced more than Cu(OH)₂ when the reaction molar ratio of sodium carbonate is low, since m is larger than n. As the reaction molar ratio of sodium carbonate increased, m is larger than n and Cu(OH)₂ was produced more than CuCO₃. In the case of m has same values as n, the optimum reaction mole ratio was 1.44 at the reaction temperature of 80℃ based on the theoretical copper content of 57.5 wt. %. The optimum amount of sodium hydroxide was 120 g at 80℃ for production of copper (II) oxide prepared by using basic copper carbonate product of first reaction. At this time, the yield of copper (II) oxide was 96.6 wt.%. Also, the chloride ion concentration was 9.7 mg/L. The properties of produced copper (II) oxide such as mean particle size, dissolution time for sulfuric acid, and repose angle were 19.5 mm, 64 second, and 34.8°, respectively. As a result of the hole filling test, it was found that the copper oxide (II) prepared with 120 g of sodium hydroxide, the optimum amount of basic hydroxide for copper carbonate, has a hole filling of 11.0 mm, which satisfies the general hole filling management range of 15 mm or less.

• Journal of Electrochemical Science and Technology
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• v.8 no.2
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• pp.146-154
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• 2017

In this study, copper (II) oxide was prepared for use in a copper electroplating solution. Copper chloride powder and copper (II) oxide are widely used as raw materials for electroplating. Copper (II) oxide was synthesized in this study using a two-step chemical reaction. Herein, we developed a method for the preparation of copper (II) oxide without the use of sintering. In the first step, copper carbonate was prepared without sintering, and then copper (II) oxide was synthesized without sintering using sodium hydroxide. The optimum amount of sodium hydroxide used for this process was 120 g and the optimum reaction temperature was $120^{\circ}C$ regardless of the starting material.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.210-211
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• 2009

In this study, we propose characteristics improvement methods according to via hole plating method for FBAR Duplexer with US PCS($T_x$:1850MHz~1910MHz, $R_x$:1930MHz~1990MHz) bandwidth which is used for wireless systems. Also, we designed and fabricated 3.8*3.8*1.8mm size microminiature FBAR Duplexer based on this proposal. First of all, in this study, we fabricated pentagon shape resonators by different size to make filter combination, and their quality factor(Q) are 687 with 6.6% of $k_{eff}^2$. Using this resonators, designed 3*2Type $T_x$ filter and 3*4Type $R_x$ filter. The transmission line, which works as phase shifter, is designed with $210{\mu}m$ in width and 18mm in length Stripline type. Inductor, which is used for matching component, is designed with width of $75{\mu}m$, a technically achievable minimum width. And adopted plating method of filling via hole with conductive epoxy for improved grounding and thermal conductivity. Using these configuration with all of the matching component values, we found Duplexer characteristics of -1.57dB ~ -1.73dB in insertion loss, -56dB in attenuation at 1850MHz~1910MHz of $T_x$ band. Also, found -2.71 dB ~ -3.23dB in insertion loss, -58dB in attenuation at 1930MHz~1990MHz of $R_x$ band.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.388-396
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• 2010

In this study, we propose characteristics improvement methods according to via hole plating method for FBAR Duplexer with bandwidth($T_x4: 1850 MHz ~ 1910 MHz, $R_x$:1930 MHz ~ 1990 MHz) which is used for wireless systems. Also, we designed and fabricated $3.8{\times}3.8{\times}1.8mm$ size microminiature FBAR Duplexer based on this proposal. First of all, in this study, we fabricated pentagon shape resonators by different size to make filter combination, and their quality factor(Q) are 687 with 6.6% of ${k_{eff}}^2$. Using this resonators, we designed $3{\times}2$ Type $T_x$ filter and $3{\times}4$ Type $R_x$ filter. The transmission line, which works as phase shifter, is designed with 210 ${\mu}m$ in width and 18 mm in length Stripline type. Inductor, which is used for matching component, is designed with width of 75 ${\mu}m$, a technically achievable minimum width. And adopted plating method of filling via hole with conductive epoxy for improved grounding and thermal conductivity. Using these configuration with all of the matching component values, we found Duplexer characteristics of -1.57 dB ~ -1.73 dB in insertion loss, -56 dB in attenuation at 1850 MHz ~ 1910 MHz of $T_x$ band. Also, found -2.71 dB ~ -3.23 dB in insertion loss, -58 dB in attenuation at 1930 MHz ~ 1990 MHz of $R_x$ band.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.2
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• pp.130-136
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• 2000

Generally, the build-up printed circuit board manufactured by the sequential process with etching, plating, drilling etc. requires many types of equipments and lead time. Etching process is suitable for mass production, however, it is not adequate for manufacturing prototype in the developing stage. In this study, we introduce a screen printing technology to prototyping a build-up printed circuit board. As for the material, photo/thermal curable resin and conductive paste are used for the formation of dielectric and conductor. The build-up structure is made by subsequent processes such as the formation of liquid resin thin layer, the solidification by UV/IR light, and via filling with conductive paste. By use of photo curable resin, productivity is greatly enhanced compared with thermal curable resin. Finally, the basic concept and the possibility of build-up printed circuit board prototyping are proposed in comparison with to the conventional process.

• Korean Journal of Materials Research
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• v.24 no.4
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.4
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• pp.51-56
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• 2003

Generally, the build-up printed circuit board manufactured by a sequential process involving etching, plating, drilling, etc, which requires many types of equipments and long lead time. Etching process is suitable for mass production, however, it is not adequate for manufacturing a prototype in the development stage. In this study, we introduce a screen printing technology for prototyping a build-up printed circuit board. As for the material, photo/thermal curable resin and conductive paste are used for the formation of dielectric and conductor. The build-up structure is made by subsequent processes such as formation of a liquid resin thin layer, solidification by a UV/IR light, and via hole filling with a conductive paste. By use of photo curable resin, productivity is greatly enhanced compared with thermal curable resin. Finally, the basic concept and the possibility of build-up printed circuit board prototyping are proposed in comparison with the conventional process.