• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of Broadcast Engineering
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• v.17 no.1
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• pp.122-128
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• 2012

Because of the system delay caused by the number of feedback retransmission in Distributed Video Coding (DVC) scheme, it is difficult to realize practical DVC in many cases. In this paper low feedback retransmission Distributed Source Coding (DSC) scheme is proposed for practical DVC scheme based on Low-Density Parity-Check (LDPC) codes because DVC system is an specific application of DSC system. This DSC scheme is achieved by using different LDPC codes optimized in each different compression rate and using source revealing scheme. Optimized LDPC codes provide us much better decoding performance which causes the 57% reduced number of iteration. Consequently, the number of feedback retransmission is decreased by 50%.