• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.70-82
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• 1993

In this paper, employing the 3-dimensional discrete cosine transform (DCT) for the utilization of the temporal correlation, an adaptive motion sequence coding technique is proposed. The energy distribution in a 3-D DCT block, due to the nonstationary nature of the image data, varies along the veritical, horizontal and temporal directions. Thus, aiming an adaptive system to local variations, adaptive procedures, such as the 3-D classification, the classified linear scanning technique and the VLC table selection scheme, have been implemented in our approach. Also, a hybrid structure which adaptively combines inter-frame coding is presented, and it is found that the adaptive hybrid frame coding technique shows a significant performance gain for a moving sequence which contains a relatively small moving area. Through an intensive computer simulation, it is demonstrated that, the performance of the proposed 3-D transform coding technique shows a close relation with the temporal variation of the sequence to be code. And the proposed technique has the advantages of skipping the computationally complex motion compensation procedure and improving the performance over the 2-D motion compensated transform coding technique for rates in the range of 0.5 ~ 1.0 bpp.

• ETRI Journal
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• v.30 no.1
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• pp.167-169
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• 2008

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode $1920{\times}1088$ 30 fps video in real time at a 30.8 MHz clock.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.89-92
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• 2000

The wireless network has bursty and high error rates. Due to the quite limited bandwidth in wireless networks, images are usually transmitted as a compressed version with VLC(variable length coding). Loss of coded data can affect a decoded image to a large extent, making concealment of errors caused by data loss an important issue. This paper presents a error concealment technique for DCT(Discrete Cosine Transform) based image coding. First, a method to estimate the missing DC coefficients of a JPEG coded image which is required for decoding the compressed image, is suggested and evaluated. Second, the missing data is interpolated by exploiting the probability of being nonzero and the correlation between adjacent blocks. In addition, since the these technique is computational efficient, it conserves system resources and power consumption, which are restrictive in mobile computers.

• ETRI Journal
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• v.31 no.5
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• pp.510-517
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• 2009

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.360-363
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• 1999

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1469-1482
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• 1993

A new image coding technique has been proposed based on the wavelet transform. To achieve lower ceding rates and good qualities in reconstructed images, some of wavelet coefficients were removed by thresholding and quantized in accordance with the sensitivity of the human visual system(HVS). For each block of subimages in wavelet transform domain, block thresholding scheme has been used to remove the unimportant wavelet coefficients according to the frequency characteristic and statistical property of wavelet coefficients. The location information of quantized blocks and removed blocks were encoded using run-length coder which is effective for the exponential distribution. Quantized coefficients were encoded using variable length coder which matches well to their distribution. Simulation results show that the reconstructed images maintain high quality with the low bit rate, below 1.0 bits per pel.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.2
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• pp.41-47
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• 2008

Most of media compression CODECs adopts the variable length coding method. This paper proposes special registers and instruction set for bit stream process in order to accelerate the decoding process of the variable length code. The instruction set shares the conventional data path to minimize additional costs. And bit stream is read from the memory instead of the special port. Therefore the instruction set minimizes the change of the processor, and is adopted without any additional input controller and buffer, and accelerate decoding process of variable length code. The data path of the instruction set needs additional 65 bits memory and 344 equivalent gates, 0.19 ns delay under TSMC $0.25{\mu}m$ technology. The instruction set reduced the execution time of the variable length code decoding process in H.264/AVC by about 55%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.59-68
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• 2005

The amount of digitalized contents has been rapidly increased, but the main distribution channel of them is Internet which is easily accessible. Therefore 'security' necessarily arises as one of the most important issues and the method of protecting contents becomes a major research topic as much as data coding techniques. In recent years, many developers have studied on techniques that allow only authorized person to access contents. Among them the scrambling method is one of well-known security techniques. In this paper, we propose a simple and effective digital video scrambling method which utilizes the intra block properties of a recent video coding technique, H.264. Since intra prediction modes are adopted in H.264 standard, it is easy to scramble a video sequence with modification of the intra prediction modes. In addition to its simplicity, the proposed method does not increase bit rate after scrambling. The inter blocks are also distorted by scrambling intra blocks only. This paper introduces a new digital video scrambling method and verifies its effectiveness through simulation.