• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.3
• /
• pp.269-281
• /
• 2014

In this paper, a systematic design of a low phase noise voltage-tuned dielectric resonator oscillator(VTDRO) using loop group delay is proposed. Designed VTDRO is closed-loop type and consists of a cascade connection of a resonator, phase shifter, and amplifier. Firstly, a reference VTDRO is fabricated and its phase noise and electrical frequency tuning range are measured. Both the phase noise and electrical frequency tuning range depend on the loop group delay. Then, a required value of loop group delay for a new VTDRO with a low phase noise can be systematically computed. In addition, its phase noise and electrical frequency tuning range can be theoretically estimated using those obtained from the measurement of the reference VTDRO. When the loop group delay increases, the phase noise decreases and the electrical frequency tuning range also decreases. The former predominantly depends on the resonator structure. Therefore we propose a systematic design procedure of a resonator with high group delay characteristics. The measured loop group delay of the new VTDRO is about 700 nsec. The measured phase noise of the new VTDRO show a state-of-the-art performance of 154.5 dBc/Hz at 100 kHz frequency offset and electrical frequency tuning range of 448 kHz for a voltage change of 0~10V. The oscillation power is about 4.39 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.10
• /
• pp.1147-1158
• /
• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.