• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.514-523
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• 2006

In this paper we propose an extended interleaving technique to improve a detailed placement. The existing row-based interleaving technique allows cells to move only within a row and it can be applied when there is no space between cells. The proposed extended-interleaving technique releases such constraints so that cells can move along with a vertical line parallel to a y-axis and space between cells is properly handled. Converged detailed-placements by a mature CAD tool have been improved by the proposed interleaving technique by 9.5% on average in half-perimeter wire length.

• Journal of Korea Society of Digital Industry and Information Management
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• v.17 no.2
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• pp.13-20
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• 2021

Placement is a very important step in the VLSI physical design process. It is the problem of placing circuit modules to optimize the circuit performance and reliability of the circuit. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for circuit placement include the cluster growth, simulated annealing, integer linear programming and genetic algorithm. In this paper we propose a adapted genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of each implementation. As a result, it was found that the adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.375-378
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• 2000

This paper discusses on application of meta-heuristic algorithms such as the genetic algorithm (GA) and the simulated annealing (SA) to the LSI module placement. We propose useful crossover method for improving of searching capability in genetic algorithm. By using our proposed crossover method, we have been able to keep good schemata in the chromosome and the variety of the solution. From the experimental results, we have obtained better result than the simulated annealing method by starting from the initial placement of the min-cut method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.147-154
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• 1989

An effective placement of macro blocks having arbitrary width and height is very important in reducing the chip area and the signal delay. In this paper, we proposed a method of macro block placement to obtain the globally optimal placement using simulated annealing, and an efficient algorithm for eliminating the overlaps between the rectangular macro blocks which may remain even after the simulated annealing process is terminated. Each macro block was enlarged to take into account minimal routing area, and these macro blocks were compacted as much as possible during the placement. This procedure was implemented in C language running on MV10000/UNIX computer system, and good placements were obtained by applying this procedure to two circuits which were consisted of 50 and 160 macro blocks respectively. Several parameters giving great effects to final placements were investigated.

• ETRI Journal
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• v.32 no.6
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• pp.932-939
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• 2010

In this paper, a fast migration method is proposed. Our method executes local relocation on a model placement where an additional module is added to it for modification with a minimum number of displacements. This method is based on mean-field annealing (MFA), which produces a solution as reliable as a previously used method called simulated annealing. The proposed method requires substantially less time and hardware, and it is less sensitive to the initial and final temperatures. In addition, the solution runtime is mostly independent of the size and complexity of the input model placement. Our proposed MFA algorithm is optimized by enabling module rotation inside an energy function called permissible distances preservation energy. This, in turn, allows more options in moving the engaged modules. Finally, a three-phase cooling process governs the convergence of problem variables called neurons or spins.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.206-210
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• 2003

In this paper, we design standard cell libraries using the 0.18um deep submircom CMOS process, and port them into a P&R (Placement and Routing) CAD tool. A simple test chip has been designed in order to verify the functionalities of the 0.18um standard cell libraries whose technical process was provided by Anam semiconductor. Through these experiments, we have found that the new 0.18um CMOS process can be successfully applied to automatic digital system design.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10c
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• pp.375-379
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• 2007

고성능 VLSI 설계 시 배치 후를 포함한 전체적인 설계 과정이 완성되기 전까지는 물리적인 정확한 설계의 특성은 배치 단계에서는 알기 어렵다. 따라서 주어진 성능 (시간적 제약조건)을 만족하는, 즉, timing-driven placement (타이밍이 고려된 배치)는 1.0 미크론 이하의 초미세한 설계에서 중요하게 되었다. 타이밍을 고려한 배치는 초기 레이아웃 디자인 단계에서 타이밍 제약조건에 의해 디자인 반복을 줄인다. 하지만 대부분의 배치 단계의 디자인 모델은 배치단계에서 기하학적인 면을 고려하여 최대허용 지연시간 (Slack 이라고 부름)과 같은 물리적인 디자인 효과를 분석하기 어려운데 이것은 물리적으로 정확한 특성이 이 단계에서 알려지지 않기 때문에 당연한 결과이다. 본 논문에서는 기하적인 요소를 고려한 Slack의 재분배의 이점을 이용하여 허용 지연시간 처리의 혁신적인 방법을 제안한다. 제안된 접근법은 timing-closed 솔루션을 쉽게 찾는데 도움을 주고 이는 디자인을 반복하는 시간을 절약할 수 있게 한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.124-130
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• 1990

This paper presents a new layout language, HAN-LALA (HANyang LAyout LAnguage), to automate the LSI/VLSI layout design. HAN-LALA is a C extension, which is easy to describe the layout. As HAN-LALA is directly compiled with no preprocessor, it renders easy debugging and short design time. For the technology independent layout design, the design rules and the process technologies are organized into seperate modules. The related objects are grouped and the placement is performed on the groups. Also the various routing modules including a river routing module and the one which can consider the forbidden regions make the layout design error-free without detailed descriptions of the layout.

• Journal of information and communication convergence engineering
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• v.8 no.6
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• pp.716-720
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• 2010

This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160{\times}192$ pixel array. The ZS algorithm is applied for a thinning stage. The logic is also synthesized in $0.35{\mu}m$ 4-metal CMOS process. The layout is performed based on an auto placement-routing and post-simulation is performed in logic level. The result is compared with a conventional one.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.853-856
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• 2005

VLSI 설계에서 셀 배치단계는 칩의 성능에 영향을 미치는 중요한 단계로서, 셀 배치문제의 주요한 목적비용으로는 배선길이, 타이밍(timing) 그리고 배선밀집도 (routing congestion)가 있다. 기존 연구에서 배선길이를 줄이기 위한 많은 기법들이 소개되었으나 배선 밀집도를 추정하고 이를 어떻게 줄일 것인가에 대한 연구는 상대적으로 많이 되어있지 않다. 본 논문에서는 셀 배치후에, 주어진 배치를 바탕으로 배선밀집도를 예측하고 배선밀집도가 높은 지역을 국부적으로 해결하는 새로운 기법을 제안한다.