• Proceedings of the Korea Information Processing Society Conference
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• 2002.11a
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• pp.433-436
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• 2002

VLSI 칩 설계는 매우 복잡한 공정이기 때문에 여러 단계, 즉 크게 분류하여 구조 설계, 논리 설계, 물리 설계 등의 과정을 거쳐 완성하게 된다. 그리고 각 단계에서는 그 단계에서 사용될 수 있는 소프트웨어의 도움을 받게 되며, 이런 소프트웨어의 도움 없이는 오늘날의 고밀도 칩 설계는 불가능하다. 각 단계에서 사용되는 소프트웨어의 주요한 기능 중 하나가 시뮬레이션 등을 통한 설계의 적합성을 테스트하는 것이라면 또 다른 주요한 기능은 설계자로 하여금 눈으로 확인하며, 변형된 설계의 일부를 눈으로 볼 수 있도록 보여주는 기능이라고 볼 수 있다. 논 본문에서는 칩 설계에서 가장 복잡한 단계라고 볼 수 있는 물리 설계 과정에 사용될 수 있는 Viewer를 설계하고 구현하여 제안한 Viewer를 통하여 회로의 정보를 보여 주며, 또한 상이한 레이아웃을 비교할 수 있도록 도와 준다. 설계된 Viewer 는 비록 초기버전이지만 물리 설계 단계에서 매우 중요한 정보, 예를 들어 critical net, 상이한 배치 등을 눈으로 확인하게 도와줌으로써 물리 설계에 관계된 다른 소프트웨어의 성능 개선을 유도할 수 있으며 또 실제 칩 설계 현장에서 바로 사용될 수 있기 때문에 실용성이 매우 높다.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.05c
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• pp.1-5
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• 2002

본 논문에서는 UART(Universal Asynchronous Receiver-Transmitter)를 soft IP(Intellectual Property) 모듈 형태로써 VLSI 설계과정을 통하여 구현하였다. 이 모듈은 현재 각종 통신 디바이스에서 최하 말단에서 직렬 데이터를 시스템으로 받아들이거나 병렬 데이터를 직렬 라인에 실어 보내는 중요한 역할을 담당한다. 본 연구에서 설계한 UART는 간단한 모듈 형태로 제작되어 있어 Verilog-HDL을 사용하여 직렬 송ㆍ수신을 필요로 하는 시스템에 내장되어 사용될 수 있다. 본 논문에서는 설계 순서에 따라 UART를 설계하고 Simulation을 하고 Synopsys Tool을 사용하여 Compile 과 Synthesis 후 Gate Area 와 Belay를 검출해 내었다. 합성결과 0.25$\mu$m 공정의 CMOS Cell Library를 사용하였을 경우 전체 면적은 1,013 gate가 나왔다. 본 논문에서 설계한 UART의 최장경로가 최대 4.12ns로 나타났으며, 최대 동작 클럭 주파수는 200MHz 로써 150Mbps 이상의 전송 속도를 가진다.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.23 no.60
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• pp.73-81
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• 2000

The testing processes for VLSI finished devices are considerably complex because they require different types of ATE to be linked together. Due to the interaction effect between two or more linked ATEs, it is difficult to trace down the cause of the unexpected longer ATE setup time and random yields, which frequently occur in the VLSI circuit-testing laboratory. The goal of this paper is to develop and demonstrate the methodology designed to eliminate the possible interaction factors that might affect the random yields and/or unexpected longer setup time as well as increase the productivity. The statistical method such as design of experiment or multivariate analysis cannot be applied to the final testing floor here directly due to the environmental constraints. Expanded product data information (PDI) is constructed by combining product data information and ATE control information. An architecture utilizing expanded PDI is designed, which enables the engineer to conduct statistical approach investigation and reduce the setup time, as well as increase yield.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.35-44
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• 2004

In this paper, we design an efficient VLSI architecture of entropy coding algorithm in JPEG2000. Entropy coder is a context-based binary arithmetic encoder, and composed of a Context Extractor(CE) and an Arithmetic Coder(AC). We speed-up CE by skipping no-operation bits in coding passes, and AC is to be performed based on MQ coder. Because of using Qe value associated with each allowed context and probability estimation, MQ coder is a multiplication free coder that reduces computation loads and makes simple the structure of arithmetic coder. We have developed and synthesized the VHDL models of CE and AC pairs using Xilinx FPGA technology. The proposed architecture operates up to 30MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.83-88
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• 2005

We propose the design method for the VLSI architecture of FNNPDS combined PDS(partial distance search) and FNNS(fast nearest neighbor search), which are used to fast encoding in vector quantization, and obtain the results that FNNPDS(fast nearest neighbor partial distance search) is faster method than the conventional methods by simulation. In simulations, we investigate timing diagrams described searching time of the nearest codevector for an input vector, and compare the average clock cycles per input vector for Lena and Peppers images. According to the result of simulations, the number of the clock cycle of FNNPDS was reduced to $79.2\%\~11.7\%$ as compared with the number using the conventional techniques.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1605-1614
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• 2008

This paper proposed a new VLSI architecture of motion estimation (ME) and compensation (MC) for efficient video compression and implemented it to hardware. ME is generally calculated using SAD result. So we proposed a new arithmetic method for SAD. The proposed SAD calculation method increases arithmetic efficiency and decreases external memory usage. Finally it increases performance of ME/MC. The proposed ME/MC hardware was implemented to ASIC with TSMC 90nm HVT CMOS library. The implemented hardware occupies about 330K gates and stably operates the clock frequency of 143MHz.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• Proceedings of the KSR Conference
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• 1998.05a
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• pp.408-418
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• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.379-382
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• 2000

We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.3
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• pp.329-333
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• 1998

본 논문에서는, LSI 적층 기술을 이용한 실시간 처리 마이크로 비젼의 개발을 소개하고 있다. 새롭게 개발된 LSI 적층기술을 이용하여, 영상신호의 증폭, 변환, 연산처리등의 기본기능을 가지는 다수의 LSI 웨이퍼를 적층한다. 각 층간의 고밀도 수직배선을 통하여 대량의 영상정보를 동시에 전달하므로써, 대규모 동시 병렬처리를 가능하게 하며, 다수의 층에 걸쳐 파이프 라인 처리가 이루어진다. VLSI 설계시스템을 이용하여, 윤곽 검출기능을 가지는 테스트 칩을 설계(2 .mu.m CMOS design rule)하고, 시뮬레이션을 통하여 양호한 동작(처리시간 10 .mu.s)을 확인하고 있다. 시험제작을 위해서는, 새롭게 개발된 LSI 적층기술이 이용된다. 영상처리의 기본회로가 실려있는 웨이퍼의 기반을 30 .mu.m 의 두께까지 연마하고, 개발된 웨이퍼 aligner를 이용하여 수직배선이 형성된 상하 두 개의 웨이퍼를 미세조정하면서 접착한다. 이상의 제작과정을 반복하여 두께 1mm이하의 인공망막과 같은 마이크로 비젼을 제작한다.