• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.119-123
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• 2002

A new modular Lateral Information Propagation Networks(LIPN) has been designed. The LIPN has shown to be useful for reconstruction of information[3]. The problem is the fact that only the small number of nodes can be implemented in a IC chip with the circuit VLSI technology. The proposed modular architecture is propagated the neural network through inter module connections. For such inter module connections, the host (computer or logic) mediates the exchange of information among modules. Also border nodes in each module have capacitors for temporarily retaining the information from outer modules. The LIPN with $4{\times}4$ modules has been designed and simulation of interpolation with the designed LIPN has been done.

• The KIPS Transactions:PartC
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• v.8C no.2
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• pp.141-154
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• 2001

MOBAS는 규칙적인 모듈로 구성되어 있어 확장이 용이하며, VLSI 구현 시 고집적화 할 수 있고, 각 모듈간에 동기를 맞추기 쉬울 뿐 아니라, 단일 종류의 칩으로 중앙 스위치 구조를 구성할 수 있다. Modified MOBAS(Multicast Output Buffered ATM Switch)는 MOBAS와 유사한 구조를 가지지만 스위치 모듈(SM : Switch Module)의 구조에서 차이를 보이며 적은 스위치소자(SWE : Switch Element)를 사용한다. 위성 통신에서 스위치의 크기뿐 아니라 고장감내 특성도 스위치를 디자인하는데 필요한 중요한 요소이다. 본 논문에서는 Modified MOBAS의 고장 특성을 분석하고 이에 적합한 Detection 기법 및 Location 기법을 제안하였다. 또한 스위치 모듈구조를 변형하여 Modified MOBAS에 비해 약간의 스위치 소자를 더 사용하지만 MOBAS에 비해서는 적은 스위치 소자를 사용할 뿐 아니라, MOBAS와 같이 단일 고장 하에서 성능의 저하가 거의 없다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.04c
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• pp.54-57
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• 2008

A new modular Lateral Information Propagation Networks can be implemented in a IC chip with the circuit VLSI technology for detection of bad materials. The proposed modular architecture is propagated the neural network through inter module connections. For such inter module connections, the host(computer or logic) mediates the exchange of information among modules. Also border nodes in each module have capacitors for temporarily retaining the information from outer modules. For detecting of Faulty Insulator, $4\;{\times}\;4$ neural network modules has been designed and simulation of interpolation with the designed networks has been done.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.9
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• pp.883-892
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• 1991

In this thesis explanation of new knapsack algorithm for public key system difficulty test and parallel architecture for implementation are suggested. Past Merkle-Hellman’s knapsack is weak in Shamir or Brickell`s attack by the effects of mapping into other easy sequenoes. But linearly shift knapsack system compensates them.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.61-71
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• 1998

Genetic Algorithm(GA) is a method of approaching optimization problems by modeling and simulating the biological evolution. GA needs large time-consuming, so ti had better do on a parallel computer architecture. Our proposed system has a VLSI-oriented interconnection network, which is constructed from a viewpoint of fractal geometry, so that self-similarity is considered in its configuration. The approach to Parallel Genetic Algorithm(PGA) on our proposed system is explained, and then, we construct the classifier system such that the set of samples is classified into weveral classes based on the features of each sample. In the process of designing the classifier system, We have applied PGA to the Traveling Salesman Problem and classified the sample set in the Euclidean space into several categories with a measure of the distance.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.144-147
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• 2000

Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.59-66
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• 1997

Neural networks has widely been be used for several practical applications such as speech, image processing, and pattern recognition. Thus, a approach to the voltage-controlled current source in areas of neural networks, the key features of CNN in locally connected only to its netighbors. Because the architecture of the interconnection elements between cells in very simple and space invariant, CNNs are suitable for VLSI implementation. In this paper, processing element of digital programmable CNN with variable template memory was implemented using CMOS circuit. CNN PE circuit was designe dto control gain for obtaining the optimal solutions in the CNN output. Performance of operation for 4*4 CNN circuit applied for fixed template and variable template analyzed with the result of simulation using HSPICE tool. As a result of simulations, the proposed variable template method verified to improve performance of operation in comparison with the fixed template method.

• ETRI Journal
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• v.13 no.2
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• pp.9-14
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• 1991

직병렬 승산기는 피승수와 승수중 어느 하나가 병렬로 입력되고 또다른 수는 직렬로 입력되는 구조를 가지며, 디지틀 신호처리, 온라인 응용, 특수 목적용 계산 시스팀 등에서 많이 이용되고 있다. 본 논문에서는 2 의 보수를 위한 직병렬 승산기의 논리구조를 제안한다. 제안한 2의 보수 직병렬 승산기는 효과적인 2의 보수 직병렬 승산 알고리즘에 의해서 모든 데이터 신호가 국부적 연결만으로 구성되며, 간단하고 모듈화된 하드웨어의 구성으로 쉽게 설계할 수 있다. 이 승산기는 무부호 승산과 마찬가지로 2n+1 사이클만을 필요로 하고, 각 사이클 시간은 무부호 직병렬 승산에 비해서 2의 보수 승산을 위한 XOR 게이트의 지연시간이 추가된 것뿐이다. 또한, 제안한 2의 보수 직병렬 승산기는 VLSI 구현에 매우 적합한 구조를 지닌다.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.