• 한국정보통신학회논문지
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• 제5권4호
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• pp.791-797
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• 2001

본 논문에서는 고속 대용량 ATM교환기에 쓰이는 스위칭소자들 중 서로 관련 있는 두 종류의 칩을 MCM기술을 이용하여 하나의 칩으로 구현하고 그 기능을 검증하였다. MCM은 소형화와 이종간 소자의 결합이 주목적으로 개발된 기술로서 하나의 패키지 상에 다양한 칩들을 실장 함으로써 칩간 지연시간이 시스템 성능향상을 가져오며 고성능화와 소형화가 시스템 개발에 도움으로 주는 기술로 각광을 받고 있는 기술이다. 고속 대용량화를 위해 구현된 MCM 스위칭 칩의 기능 검증을 위하여 기존에 개발된 칩들의 VHDL코드를 가지고 시뮬레이션 모델을 생성하였고, 시뮬레이션을 통해 모델링된 패턴의 입출력 값을 얻었다. 칩 테스트 장비에 패턴 값을 입력하여 시뮬레이션 결과와 비교함으로써 동작성능을 평가하였다. 본 연구에서 실행된 시뮬레이션은 SUN 워크스테이션 상에서 Synopsys툴을 사용하였고, 칩의 기능 시험은 Trillium장비를 사용하였다. 본 연구를 통하여 시뮬레이션을 통해 얻은 결과와 시험장비를 통해 얻은 결과를 비교한 결과 처음에 목적한 패턴의 시험에 대한 기능들이 일치됨을 알았다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.205-208
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• 2000

In this paper, we have designed a pager based on the FLEX protocol. The pager consists of a decoder, a MCU, a SPI, and a User interface. The decoder contains the following blocks： synchronizer, de-interleaver, error corrector, packet builder. The decoded data is converted to SPI packets for communication between the MCU and the FLEX decoder. The host MCU is a RISC pipelined architecture, so it processes data at high speed and also sends messages to user interface. We have designed the proposed pager as structural modeling using VHDL language. Then, We simulated and synthesized it using tool of SYNOPSYS corporation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.369-374
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• 2016

This paper presents a design procedure of an integrated inductor with a magnetic core for power converters. This procedure considerably reduces design time and effort. The proposed design procedure is verified by the development of an inductor model dedicated to the monolithic integration of DC-DC converters for portable applications. The numerical simulation based on the FEM (finite elements method) shows that 3D modeling of the integrated inductor allows better estimation of the electrical parameters of the desired inductor. The optimization of the electrical parameter values is based on the numerical analysis of the influence of the geometric parameters on the electrical characteristics of the inductor. Using the VHDL-AMS language, implementation of the integrated inductor in a micro Buck converter demonstrate that simulation results present a very promising approach for the monolithic integration of DC-DC converters.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.67-70
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• 1999

DS-CDMA is used to widely spread spectrum for a cellular mobile digital communication that maximizing users- capacity at the limited frequency bandwidth, solving technical matters with the channel. Especially, the capability of a spread spectrum receiver relied on fast code acquisition time at the demodulation. In this paper, we considered that fast code acquisition time when a spread spectrum system is designed, and existed code acquisition system set up one code epoch on a position at initial processing, but the proposed code acquisition system improved that two code epoch are set up at the same time, therefore code acquisition time is diminished in effect. The structure modeling to VHDL language. Its synthesized the synthesized and, is implemented FPGA chip

• 한국통신학회논문지
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• 제23권6호
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• pp.1433-1442
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• 1998

The thesis presents a dual audio decoder which can decode both AC-3 and MPEG-2 bitstream. The MPEG-2 synthesis processi s optimized via FFT to establish the common data path with AC-'3s. A dual audio decoder consists of a DSP core which performs the control-intensive part of each algorithm and a common synthesis filter which perfomrs the computation-intensive part. All the components of the dual audio decoder have been described in VHDL and simulated with a SYNOPSYS tool. The software modeling of the DSP core was used for functional validation. After being synthesized using 0.6 .mu.m-3ML technology standard cell, the dual audio decoder was simulated at gate-level with a COMPASS tool for hardware validation.

• 한국시뮬레이션학회논문지
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• 제9권2호
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• pp.15-25
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• 2000

Since data security problems are very important in the information age, cryptographic algorithms for encryption and decryption have been studied for a long time. The GOST(Gosudarstvennyi Standard or Government Standard) algorithm as a data encryption algorithm with a 256-bit key is a 64-bit block algorithm developed in the former Soviet Union. In this paper, we describe how to design an encryption chip based on the GOST algorithm. In addition, the GOST algorithm is compared with the DES(Data Encryption Standard) algorithm, which has been used as a conventional data encryption algorithm, in modeling techniques and their performance. The GOST algorithm whose key size is relatively longer than that of the DES algorithm has been expanded to get better performance, modeled in VHDL, and simulated for implementation with an CPLD chip.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2000년도 춘계학술대회 논문집
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• pp.336-343
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• 2000

This paper proposes the failsafe control logic. which has applied to the voting on the TMR system by using FPGA The self-detection circuit is also designed for detecting a characteristic of fault at TMR system. The fault producing in the self-detection system is largely classified among an intermittent fault, a transient fault and a permanent fault. If it is happened to the permanent fault, the system can be failed. Therefore, it is designed the logic circuit which is not transferred the permanent fault to the system after shut off output. The control logic of the Fail Safe proposed in the paper is required for a circuit integrate of device to minimize the failure happened. Therefore, it makes to design FPGA with modeling of VHDL. The circuit of the Fail Safe of TMR system is able to apply to nuclear system, rail-way system, aerospace and aircraft system which is required for high reliability.

• 전자공학회논문지A
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• 제33A권10호
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• 한국정보과학회논문지:시스템및이론
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• 제29권1호
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• pp.42-56
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• 2002

WHDL이나 Verilog와 같은 기존의 하드웨어 기술 언어(Hardware Description Language)를 이용하여 비동기 마이크로세서를 모델링하고 시뮬레이션을 수행할수 있으나 핸드셰이크 프로토콜 (handshake protocol) 에 의해 동작하는 비동기 마이크로프로세서의 기술이 지나치게 복잡해진다. 결과적으 로 성능 평가 시간이 너무 길어져 상위 수준(system level)에서의 효과적인 설계 공간 탐색에 많은 어려움을 겪는다. 따라서 상위 수준에서 비동기적 특성인 핸드 셰이크 프로토콜을 쉽게 모델링하고 빠른시간 내에 효과적으로 시뮬레이션할수 있는 방법론과 도구가 필요하다. 이런 목적 하에 프로세서 모델링과 시 뮬레이션을 통하여 성능 평가를 수행할수 있는 자동화 도구 SLEDS(System Level Event Driven Simulator)를 개발하였다. 본 도구의 궁극적 목표는 프로세서를 구성하는 모듈들의 지연을 조절하여 (delay balancing)전체적으로 프로세서가 고성능을 얻을수 있도록 최적화 조건을 구하는 것이다. 이와 더불어 정의된 행위를 실제로 수행함으로써 예상한 결과와 실제 결과를 비교하여 설계가 제대로 되었는지 상위 수준에서의 검증을 목표로 한다.