• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.27-32
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• 2013

In this paper, the boost converter was implemented by digital control in many applications of the step-up. The PWM(pulse width modulation) control module of boost converter was digitized at power converter using the FPGA device and VHDL. The boost converter was designed to output a fixed voltage through the PI control algorithm of the PWM control module even if input voltage and output load are variable. The boost converter was digitized can be simplified by reducing the size of the module and the external control components. Thus, the digital power IC has advantageous for weight reduction and miniaturization of electronic products because it can be controlled remotely by setting the desired output voltage and PWM control module. The boost converter using the digital power IC was confirmed through experiments and the good performances were showed from experiment results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2484-2491
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• 2009

This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.585-588
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• 2002

In this paper, the current controlled active poler filter(APF) with the performance of reducing harmonic and improving power factor is studied. It has high speed and good performance with low cost. The current controlled shunt APF is proposed, and the control part of APF is designed of SOC(System On Chip). So this system has low expense and good performance. In this study, the micro-controller which designed with VHDL. is applied to APF system. And the proposed technique in this paper demonstrates the excellent of the dedicated micro-controller. VHDL-based ASIC can simplify the process of development and has a competition in market because it reduces the consuming time for the design of IC(Integrated Circuit) in system level.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.657-660
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• 2002

In this paper, the FFT processor for power measurement using VHDL (Very high-speed integrated circuit Hardware Description Language) is discussed. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the Input signal. The proposed system is based on FFT Processor which is designed using VHDL. In the design of FFT processor, $radix-2^2$ is adopted to reduce several complex multipliers for twiddle factor. And this processor adopt pipeline structure. Therefore, the system Is able to have both high hardware efficiency and high performance.

• The Transactions of the Korea Information Processing Society
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• v.7 no.11
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• pp.3556-3565
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• 2000

가상 프로토타입(Virtual Prototyping: VP) 방법론을 이용하면 내장형 시스템을 설계하고 구현할 때에 비용을 절감하면서 제품의 개발기간을 단축할 수 있다. VP는 S/W component, H/W component 그리고 S/W 와 H/W를 연결하는 Interface component로 구성되어 진다. VP의 구성 요소중 H/W component를 구현하는 방법은 여러 가지가 있었으나 시스템 명세 언어로부터는 하드웨어 컴포넌트로 구현하는 방법을 고려하고자한다. 그러나 시스템 명세 언어로부터 생성된 H/W component 용 VHDL 코드는 항상 합성 가능한 코드라고 할 수 없다. 본 논문에선 시스템 명세 언어로부터 검증을 용이하게 하는 하드웨어 구현을 위하여 명세언어로써 SpecCharts를 이용하고 이로부터 동기적 의미론을 만족하는 합성 가능한 VHDL 코드를 생성하는 방법론을 제시한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.908-911
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• 2002

본 논문에서는 영상의 불법적인 복사를 방지하기 위해 사용되는 워터마킹을 내장한 JPEG 압축용 DCT의 VHDL 모델을 제시한다. 워터마킹 방법은 사람의 시각 시스템을 이용하여 주파수 영역에서 영상의 시각적인 특성에 적응하는 워터마크를 내장한다. 영상 압축시에 주파수 영역으로 변환해주는 DCT와 함께 화질저하에 대한감소와 공격에 강한 water marking을 구현함으로서 손실 압축에서도 방지 기능을 유지하면서 시스템의 효율적인 구성을 얻을 수 있다. 구현된 DCT의 VHDL 모델을 사용한 시뮬레이션 결과 고주파 성분이 많은 복잡한 영상과 저주파 성분이 많은 단순한 영상에 적용하여 워터마크가 시각적으로 보이지 않고 JPEG 손실압축과 잡음에도 견고함을 가지며, 기능을 추가하여도 기존에 비해 면적을 적게 차지하여 빠른 속도를 얻을 수 있어, 소형 시스템에 솔루션에 적용이 적합하다.

• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.71-76
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• 2014

This paper presents the implementation for the BLDC motor speed control system using VHDL and FPGA. The BLDC motor is widely used in automation for its good robustness and easy controllability. In order to control the speed of the BLDC motor, the PI controller used for static RPM output of the BLDC motor to variations in load. In addition, by using the DA converter, we were able to monitor the BLDC motor reference speed and the current speed through real time. The motor speed command and the parameters of the PI speed controller were modified easily by the FPGA and the AD converter. Finally, in order to show the feasibility of the control algorithm the speed control characteristics of the motor was monitored using an oscilloscope and the DA converter. Further, the speed control system was designed in this paper has shown the applicability of the drive system of the factory automation.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.398-400
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• 1996

We present the implementation of the adaptive filter for EMG signal processing using VHDL. For making ASIC, the basic FPU(floating point processor), e.g., adder, multiplier and divider, are implemented with VHDL. The FPU is simulated and the controller for the RLSL(recursive least square lattice) algorithm of the adaptive filter is implemented. Then FPU and the controller are linked and simulated. Finally the models are synthesized and the gate level is implemented.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.69-83
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• 1998

In this paper, we present the results of simulation by running parallel VHDL simulation on typical MPP(Massively Parallel Processor) systems such as IBM SP2 and SGI Origin 2000. Parallel simulation uses the synchronous protocol and parallel program is implemented using MPI(Message Passing Interface) based on message passing model, so that it can urn on any parallel programming environment which supports MPI, a standard communication library. And then GVT(Global Virtual Time) computation for parallel simulation is based on the global broadcasting with MPI＿Bcast(), which is a standard function in MPI and piggybacking. Our benchmark exhibits that as size of VHDL grows, the parallel simulation has a better performance compared with the sequential simulation. In addition, we also show the results of comparison between IBM SP2 and SGI Origin 2000 by applying the same application to those indirectly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1311-1319
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• 2007

This paper presents the VHDL implementation procedure of the passive RFID tag operating in Ultra High Frequency. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of an interrogation rate. In order to satisfy linking time, the pipe-line structure is used, which can minimize latency to serial input data stream. We also propose the sampling strategy to decode the Preamble, the Frame-sync and PIE symbols in reader commands. The simulation results with the fastest data rate and multi tags environment scenario show that the VHDL implemented tag performs faster operation than GEN2 proposed.