• Title/Summary/Keyword: VDM(Vienna Development Method)

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The Conversion of a Set, a Sequence, and a Map in VDM to a Linked List in a Programming Language (VDM의 자료구조인 set, sequency, map의 프로그래밍 언어 자료구조인 linked list로의 변환)

  • Yu, Mun-Seong
    • The KIPS Transactions:PartD
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    • v.8D no.4
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    • pp.421-426
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    • 2001
  • A formal development method is used to develop software rigorously and systematically. In a formal development method, we specify system by a formal specification language and gradually develop the system more concretely until we can implement the system. VDM is one of formal specification languages. VDM uses mathematical data structures such as sets, sequences, and maps to specify the system, but most programming languages do not have such data structures. Therefore, these data structures should be converted. We can convert mathematical data structures in VDM to a linked list, a data structure in a programming language. In this article, we propose a method to convert a set, a sequence, and a map in VDM to a linked list in a programming language and prove the correctness of this conversion mathematically.

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Formal description and reference implementation generation of MD4 message digest algorithm (MD4 해쉬알고리즘의 형식적 표현과 참조구현 코드 생성)

  • 김기수;김영화;염창선;류재철
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 1995.11a
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    • pp.126-137
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    • 1995
  • VDM-SL(Vienna Development Method - Specification Language)은 다양한 표준들의 정확한 기술을 위해 제시되고 있는 형식규격어의 하나로서 특히 보안표준의 표현에 적합한 형식규격어이다. 이러한 VDM-SL을 사용하여 보안표준의 표현 및 실행코드 생성의 정확성과 편리성을 제공하기 위한 다양한 도구들이 개발되고 있으며 이들 중 IFAD VDM-SL Toolbox는 가장 많은 기능을 구진 도구이다. 본 논문에서는 IFAD WDM-SL Toolbox를 이용해 해쉬알고리즘의 하나인 MD4 Message Digest Algorithm을 형식적 표현기법으로 나타내고 이를 바탕으로 참조구현 코드를 C++로 생성하는 방법을 설명한다. 또한 형식적 표현기법과 IFAD VDM-SL Toolbox를 이용해 생성된 참조구현코드의 실행 결과를 MD4의 테스트 벡터 (test vector)를 이용하여 RSA사에서 구현한 MD4 알고리즘과 비교 분석하여 형식적 표현기법을 이용하여 생성된 코드의 활용성에 대해 설명하고자 한다.

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Formal Description and Reference Implementation Code Generation for a Security Algorithm using VDM-SL (VDM-SL을 이용한 보안 알고리즘의 형식적 표현과 참조구현 코드 생성)

  • Kim, Young-Gil;Kim, Ki-Su;Kim, Young-Wha;Ryou, Jae-Cheol;Jang, Chung-Ryong
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.6 no.4
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    • pp.67-84
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    • 1996
  • VDL-SL (Vienna Development Method-Specification Language) is one of the FSL(Formal Specification Language) which is being presented for the correct description of the security relevant standards. Several tools are being developed for the correctness and the convenience in the description and executable code generation of security relevant standards using VDM-SL. The IFAD VDM-SL Toolbox is one that has many functions : syntax checking, type checking, c++ code generation, test coverage information. This paper describes a formal method for description and implementation of MD4 algorithm using VDM-SL and IFAD VDM-SL Toolbox, and examines the result applied to secure hash algorithm, and proposes the relation to strict conformance test which recently suggested as a security test method.

Specification and Simulation Environment for Prototying the Object Model (객체 모델의 프로토파이핑을 위한 명세 및 시물레이션 환경)

  • Jung, Lan;Kim, Jung-A;Moon, Chung-Ryeal;Kim, Jung-Doo
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.5
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    • pp.1243-1256
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    • 1997
  • Object modeling has been cinsidered as an efficient technique for eleciting user requirements and communicat-ing between developers and customers. But model itself is not easy to understand what recult will be after coding and whether it will be meet with the requirements of customers. In this paper, we developed the envuroment for visualization of object model for validating with rewuirnent at the early stage. Therefore, we defined correct and complete rules which can transform the object model.the delierables of Shler/Mellor's method, into a for-mal specification language of VDM(Vienna Development Methods) with a mathematical basis. This basis provides the means of proving that a specification is realizable and proving properties of a system.Therefore.the completeness, preciceness of object model can be verified by proving the transformed VDM specification and prototyping by constructing a visualization supporting enviroment.

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