• 제목/요약/키워드: Unit Tasks

검색결과 252건 처리시간 0.034초

중학교 삼각비 단원 과제의 수학적 연결성 구성요소 분석 및 교사의 인식과 실천적 방안 조사 (Analysis of mathematical connection components of the trigonometric ratio tasks in middle school and survey of teachers' perceptions and practical measures)

  • 최윤정;오영석;김동중
    • 한국수학교육학회지시리즈A:수학교육
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    • 제63권1호
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    • pp.63-83
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    • 2024
  • 본 연구의 목적은 2015 개정 수학과 교육과정의 중3 교과서 삼각비 단원에 포함된 과제의 수학적 연결성 구성요소를 분석하고 이에 대한 교사의 인식 및 실천적 방안을 조사하는 것이다. 이를 위하여 중학교 3학년 수학교과서 9종을 대상으로 삼각비 단원에 포함된 수학적 연결성 과제의 특징을 분석하고, 이에 대한 인식과 실천적 방안을 조사하기 위해 예비 연구에서 현직 수학 교사 1인, 본 연구에서 현직 수학 교사 2인을 대상으로 설문지 조사와 인터뷰를 진행하였다. 연구 결과, 중학교 3학년 삼각비 단원에서는 외적 연결성의 과제가 내적 연결성의 과제보다 적은 것으로 나타났다. 또한 교사의 인식 및 실천적 방안에서는 교사의 관점에 따라 과제에 포함된 수학적 연결성에 대한 분석이 다르게 나타났으며, 이에 따른 실천적 방안 또한 다양하게 나타났다. 이러한 연구 결과는 학생들의 효과적인 수학적 연결성 함양을 위해 수학 과제, 교사의 인식, 교사의 실천적 방안 사이의 관계성을 밝혔다는 점에서 의의가 있다고 볼 수 있다.

원자로 제어봉 구동장치 제어시스템용 전력제어기 FPGA 설계 (Design of FPGA in Power Control Unit for Control Rod Control System)

  • 이종무;신종렬;김춘경;박민국;권순만
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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    • pp.563-566
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    • 2003
  • We have designed the power control unit which belongs to the power cabinet and controls the power supplied to Control Rod Drive Mechanism(CRDM) as a digital system based on Digital Signal Processor(DSP). The power control unit dualized as the form of Master/Slave has had its increased reality. The Central Process Unit(CPU) board of a power control unit possesses two Digital Signal Processors(DSPs) of the control DSP for performing the tasks of power control and system monitoring and the communication of the Control DSP and the Communication DSP. To accomplish the functions requested in the power control unit effectively, we have installed Field Programmable Gate Arrays(FPGAS) on the CPU board and have FPGAs perform the memory mapping, the generation of each chip selection signal, the giving and receiving of the signals between the power controllers dualized, the fault detection and the generation of the firing signals.

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Facial Action Unit Detection with Multilayer Fused Multi-Task and Multi-Label Deep Learning Network

  • He, Jun;Li, Dongliang;Bo, Sun;Yu, Lejun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제13권11호
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    • pp.5546-5559
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    • 2019
  • Facial action units (AUs) have recently drawn increased attention because they can be used to recognize facial expressions. A variety of methods have been designed for frontal-view AU detection, but few have been able to handle multi-view face images. In this paper we propose a method for multi-view facial AU detection using a fused multilayer, multi-task, and multi-label deep learning network. The network can complete two tasks: AU detection and facial view detection. AU detection is a multi-label problem and facial view detection is a single-label problem. A residual network and multilayer fusion are applied to obtain more representative features. Our method is effective and performs well. The F1 score on FERA 2017 is 13.1% higher than the baseline. The facial view recognition accuracy is 0.991. This shows that our multi-task, multi-label model could achieve good performance on the two tasks.

차량용 임베디드 프로세서에서 저전력 반응적 제어를 위한 이기종 멀티코어 협력적 스트리밍 온-칩 소프트웨어 구조 (Collaborative Streamlined On-Chip Software Architecture on Heterogenous Multi-Cores for Low-Power Reactive Control in Automotive Embedded Processors)

  • 권지수;박대진
    • 대한임베디드공학회논문지
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    • 제17권6호
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    • pp.375-382
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    • 2022
  • This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

에어밸런서 공압 회로의 설계 및 성능 실험 (Pneumatic circuit design and Performance test of Air balancer)

  • 김동수;배상규
    • 유공압시스템학회논문집
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    • 제3권3호
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    • pp.20-24
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    • 2006
  • Air balancer is a conveyance cargo-handling machine, used in assembly and process lines of car and machining industries. This can lift up an object, the weight of which is from 5 to 200 kg, and moves it to a position. As industrial technologies evolve, it is required to move an object and fit it into a specified position with greater accuracy, rather than performing simple tasks such as lifting objects up and down as conventional ones do. There is also a demand to handle an object with one hand, rather than with two hands,. Through designs of manifold unit for an air balancer function, pilot regulator unit to keep pressure constant, hand unit for an accurate load perception function, and air balancer circuit, this study enables everybody to work it with ease and convenience. Experiments and comparisons were conducted for the performance evaluation of the circuit.

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페트리네트 기반 관리 제어시스템의 설계 (Design of A Petrinet-based Supervisory Control System)

  • 공성학;서일홍
    • 대한전기학회논문지:시스템및제어부문D
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    • 제54권8호
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    • pp.486-494
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    • 2005
  • This paper presents a design experience of a supervisory control system. For effective programming of job commands, a petri net-type graphical language (PGL) is proposed applied to various tasks having concurrency and synchronization. Our PGL based supervisory control system is composed of PGL editor and PGL compiler; PGL editor is designed to help us to generate a job program using graphical symbols. PGL compiler includes analyzer, scheduler, and tranlator, PGL analyzer prevents a deadlock or resource allocation of unit cell, PGL scheduler generates a adequate job sequence of unit cell. and PGL translator translate the scheduled sequence into the iob program of each unit cell.

Robot Ergonomics의 일환으로서 로봇 작업측정에 관한 연구 (Work Measurement in Robot Ergonomics)

  • 권규식
    • 산업경영시스템학회지
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    • 제21권48호
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    • pp.201-211
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    • 1998
  • The fundamental object of work measurement is to precisely establish the time standards, which are the indices of labor productivity. This study discussed the development of robot work measurement method that could establish the time standard effectively. In manufacturing industries the various robot tasks are generally classified and standardized by the unit motions. The Robot Modularization of the Unit Motion (ROMUM) was realized by the module of two steps GET and PUT unit motions. This method reduced time and effort of analysis, and could be done with ease. Therefore, ROMUM will increase the convenience of use for the unskilled worker and decrease the time required, cost and errors. And, it will contribute to reduce the unnecessary motion by robot motion analysis.

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마스크/논리 연산에 효율적인 H/W 구조를 갖는 영상 데이터 처리장치 (An image data processing unit of efficient H/W structure for mask/logic operations)

  • 이상현;김진헌;박귀태
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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    • pp.685-691
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    • 1993
  • This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

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Payload Management Unit design of MSC (Multi-Spectral Camera)

  • Kong, Jong-Pil;Yong, Sang-Soon;Heo, Haeng-Pal;Kim, Young-Sun;Park, Jong-Uk;Youn, Heong-Sik
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2003년도 Proceedings of ACRS 2003 ISRS
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    • pp.1108-1110
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    • 2003
  • MSC(Multi-Spectral Camera) which is a unique payload for KOMPSAT-2, comprises main three subsystems of PMU(Paylaod Management Unit), EOS(Electro -Optical Subsystem) and PDTS(Payload Data Transmission Subsystem). The PMU, as a main controller of MSC, performs major tasks such as interfacing with S/C(Space Craft), controlling the MSC operation, distributing and controlling of operating power to all MSC including thermal unit, etc. In this paper the H/W configurations as well as the functions of PMU are introduced and possible changes for the future development are suggested.

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