• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.537-542
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• 1998

Logic functions such as fuzzy switching functions and multiple-valued Kleenean functions, that are models of Kleene algebra have been studied as foundation of fuzzy logic. This paper deals with a new kinds of functions-fuzzy switching functions with constants-which have features of both the above two kinds of functions . In this paper, we propose new canonical forms for enumerating them. They are much useful to estimate simply the number of fuzzy switching functions with constants.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.689-691
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• 1995

In this paper, a fault detection and isolation unit(FDIU) for a centrifugal pump system driven by DC-motor is proposed. The proposed scheme can be classified into the dedicated observer scheme(DOS). A fuzzy logic based inference engine is adopted for the isolation of each faults. Having the fuzzy inference engine, the proposed FDIU resolve a few important problems of the conventional DOSs with conventional two valued logic. The ouputs of the proposed FDIU are not "ith fault occurred" but the grade of memberships that indicate the consistency of observered symptoms(residuals) with each fault symptoms stored in the rule base. The ouputs can easily be transferred to the ranking of the fault possibilities and it will provide very useful informations in monitoring the process. The simulation results show that the FDIU has very good diagnostic ability even in the noisy environment.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.31-39
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• 1990

An optimization problem of AND-EXOR PLA's with input decoders can be regarded as a minimization problem of Exclusive-Or Sum-Of-Products expressions (ESOP's) for multiple-valued input two-valued output functions. In this paper, We propose a minimization algorithm for ESOP's. The algorithm is based on an iterative improvement. Five rules are used to replace a pair of products with another one. We minimized many ESOP's for arithmetic circuits. In most cases, ESOP's required fewer products than SOP's to realized same functions.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.102-109
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• 2001

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

• Journal of KIISE:Software and Applications
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• v.26 no.8
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• pp.1010-1017
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• 1999

불완전한 계획 영역 이론은 오류 영역(noisy domain)에서 하나의 상태에 상반된 연산자들이 적용되는 불일치성 문제를 야기할 수 있다. 이 문제를 해결하기 위해서 본 논문은 상태를 기술하기 위해 다치 논리를 도입하여 제어지식으로서의 부정적 선행조건을 학습하는 새로운 방법을 제안한다. 기계에는 알려지지 않은 이러한 제어지식이 인간에게는 반대개념으로 잠재적으로 사용되고 있다. 이러한 잠재된 개념을 학습하기 위해 본 논문은 반대 연산자들로 구성된 사이클을 영역이론으로부터 기계적으로 생성하고, 이 연산자들에 대한 실험을 통해 반대 리터럴(literal)들을 추출한다. 학습된 규칙은 불일치성을 방지하면서 동시에 중복된 선행조건을 제거하여 연산자를 단순화시킬 수 있다.Abstract An incomplete planning domain theory can cause an inconsistency problem in a noisy domain, allowing two opposite operators to be applied to a state. To solve the problem, we present a novel method to learn a negative precondition as control knowledge by introducing a three-valued logic for state description. However, even though the control knowledge is unknown to a machine, it is implicitly known as opposite concept to a human. To learn the implicit concept, we mechanically generate a cycle composed of opposite operators from a domain theory and extract opposite literals through experimenting the operators. A learned rule can simplify the operator by removing a redundant precondition while preventing inconsistency.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• Journal of IKEEE
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• v.15 no.4
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• pp.354-362
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• 2011

One of the unsolved problems in Artificial Neural Networks is related to the capacity of a neural network. This paper presents a CoreNet which has a multi-leveled input and a multi-leveled output as a 2-layered artificial neural network. I have suggested an equation for calculating the capacity of the CoreNet, which has a p-leveled input and a q-leveled output, as $a_{p,q}=\frac{1}{2}p(p-1)q^2-\frac{1}{2}(p-2)(3p-1)q+(p-1)(p-2)$. With an odd value of p and an even value of q, (p-1)(p-2)(q-2)/2 needs to be subtracted further from the above equation. The simulation model 1(3)-1(6) has 3 levels of an input and 6 levels of an output with no hidden layer. The simulation result of this model gives, out of 216 possible functions, 80 convergences for the number of implementable function using the cot(x) input leveling method. I have also shown that, from the simulation result, the two diverged functions become implementable by precalculating the weight values. The simulation result and the precalculation of the weight values give the same result as the above equation in the total number of implementable functions.