• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.217-221
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• 2003

In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-OFDM. The proposed Viterbi decoder is conceptually same as the multiple Phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency. Also, the proposed algorithm can be used in the single carrier modulation.

• Information and Communications Magazine
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• v.18 no.6
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• pp.119-125
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• 2001

1990년 초반부터 송신 다이버시티에 대한 연구가 있어 왔다. 1990년 후반부터는 송수신 다이버시티에 대한 실용적인 결과가 부호 이론과 접목이 되면서 나오기 시작한다. 그 중에서 매우 유용한 결과인 Space-Time 부호에 대하여 다룬다. 본 논문에서는 직교 Space-Time block code. Layered Space-Time processing, 그리고 Space-Time trellis Coding의 세 가지로 분류하여 내용을 정리한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2000.11b
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• pp.3-8
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• 2000

본 논문에서는 고품질의 DTV, HDTV와 인터넷 등의 고속 광대역 멀티미디어 서비스를 위한 HFC(Hybrid Fiber Coaxial)-CATV망의 상향채널을 SPW(Signal Processing Worksystem)를 사용하여 모델링하고, HFC-CATV망 상향채널의 문제점인 유입잡음의 영향을 전산모의 실험을 통해 분석하였다. 그리고 상향채널의 열악성을 극복할 수 있는 방법으로 트렐리스 부호화 변조(Trellis-Coded Modulation)와 OFDM(Orthogonal Frequency Division Multiplexing)을 결합한 OFDM-TC8PSK 시스템을 제안하고 그 성능을 CATV 상향채널 환경에서 전산모의 실험하고 기존의 QPSK 시스템의 성능과 비교 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.11
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• pp.650-656
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• Journal of Navigation and Port Research
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• v.36 no.10
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• pp.845-849
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• 2012

The next-generation wireless communication requires fast transmission speeds with various services and high reliability. In order to satisfy these needs we study MIMO system used layered space time coded system (LST) combining space time trellis codes (STTC) with turbo codes. In LST, two codes that are inner and outer codes are concatenated in the serial fashion. The inner codes are turbo Pi codes suggested in DVB-RCS NG system, and outer codes are STTC codes proposed by Blum. The interleaver technique is used to efficiently combine two codes. And we proposed and simulated that a full iteration method between turbo decoder and BCJR decoder to improve the performance instead of only processing inner-iteration turbo decoder. The simulation results of proposed effective layered method show improving BER performance about 1.3~1.5dB than conventional one.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.6
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• pp.746-760
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• 1998

In this paper, an adaptive RSSD(reduced-state sequence detection) receiver is proposed for the purpose of reducing the complexity and decision delay of the adaptive MLSD(maximum-likelihood sequence detection) receiver in the mobile satellite channel. The RSSD receiver reconstructs the trellis with a reduced number of states. The performance degradation due to the reduced states is compensated by modifying the branch metric calculation which uses the symbols in each path memory to estimate the residual ISI(intersymbol interference) terms. The structure of the proposed adaptive RSSD is a modified RSSD utilizing a per-survivor processing as well as the symbol-aided method and a channel estimation using the tentative data sequences. The complexity and performance of the proposed adaptive RSSD are controlled by the number of system states and ISI cancelers and the inserting period of the known symbols. In spite of a suboptimal alternative receiver compared to the adaptive MLSD receiver, the proposed adaptive RSSD receiver is able to reduce the complexity significantly and track the time-varying channel fast and reliably.

• Korean Journal of Food Science and Technology
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• v.52 no.3
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• pp.284-289
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• 2020

The cultivars of wine grapes 'Doonuri', 'Narsha', 'Cabernet Sauvignon', and 'Merlot' were cultivated in Modified-T (MT), Modified-T Cane pruning (MTC), and Geneva Double Curtain (GDC) trellises, and the changes in vine growth, fruit and wine characteristics were compared for two years (2018 and 2019). With respect to the vine growth characteristics, the wine grape cultivars cultivated in the GDC trellis were significantly inferior to those cultivated in the MT or MTC trellises. The grape yields of the cultivars cultivated in GDC trellise increased by 1.5 to 2 times cultivated in the GDC trellises compared to those cultivated in the other trellis, however, the fruit characteristics (total soluble solids, titratable acidity, and berry weight) did not differ among the differently cultivated groups. Moreover, the anthocyanin content and red color of the wine were significantly enriched in all red wine grape cultivars cultivated in the GDC trellises.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.777-780
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• 2003

We have tried to create a vision system like human eye for a long time. We have obtained some distinguished results through many studies. Stereo vision is the most similar to human eye among those. This is the process of recreating 3-D spatial information from a pair of 2-D images. In this paper, we have designed a stereo matching algorithm based on systolic array architecture using edges and pixel data. This is more advanced vision system that improves some problems of previous stereo vision systems. This decreases noise and improves matching rate using edges and pixel data and also improves processing speed using high integration one chip FPGA and compact modules. We can apply this to robot vision and automatic control vehicles and artificial satellites.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.4
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• pp.11-16
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• 2004

A simple stopping criterion for iterative decoding based on min-sum processing is presented. While most stopping criteria suggested in the literature, are based on Cross Entropy (CE) and its simplification, the proposed stopping criterion is to check if a decoded sequence is a valid codeword along the encoder trellis structure. This new stopping criterion requires less computational complexity and saves mem4)ry compared to the conventional stopping rules. The numerical results are presented on the 3GPP turbo code and a Serially Concatenated Convolutional Cods (SCCC).