• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.9
• /
• pp.1359-1368
• /
• 1989

In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2002.10a
• /
• pp.235-240
• /
• 2002

In micro-EBM, it is well blown that RC circuit is suitable for discharge circuit because of its low pulse width and relatively high peak current. To increase machining speed without changing unit discharge energy, charge resistance should be decreased. But, if very low, continuous (or normal) arc discharge occurs, then increases electrode wear and reduces machining speed remarkably. In this paper, RC circuit with transistor is used to micro-EDM. Experimental results show that RC circuit with transistor can cut off continuous (or normal) arc discharge effectively if duty factor and switching period of transistor are set up optimally. Through experiments with varying charge resistance, it can be known that RC circuit with transistor has about two times faster machining speed than that of RC circuit. Especially, it has prominent rise-effect of machining speed in low unit discharge energy, so that a high-quality and high-speed micro-EDM can be realized through RC circuit with transistor.

• Journal of the Semiconductor & Display Technology
• /
• v.16 no.3
• /
• pp.59-64
• /
• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.163-166
• /
• 2004

모바일향 90nm DRAM을 개발하기 위하여 비대칭 채널 구조를 갖는 Recess Channel Array Transistor (RCAT)로 cell transistor를 구현하였다. DRAM cell transistor에서 junction leakage current 증가는 DRAM retention time 열화에 심각한 영향을 미치는 요인으로 알려져 있으며, DRAM의 minimum feature size가 점점 감소함에 따라 short channel effect의 영향으로 junction leakage current는 더욱 더 증가하게 된다. 본 실험에서는 short channel effect의 영향에 의한 junction leakage current를 감소시키기 위하여 Recess Channel Array Transistor를 도입하였고, cell transistor의 채널 영역을 비대칭으로 형성하여 data retention time을 증가시켰다. 비대칭 채널 구조을 이용하여 Recess Channel Array Transistor를 구현한 결과, sub-threshold 특성과 문턱전압, Body effect, 그리고, GIDL 특성에는 큰 유의차가 보이지 않았고, I-V특성인 드레인 포화전류(IDS)는 대칭 채널 구조인 transistor 대비 24.8% 정도 증가하였다. 그리고, data retention time은 2배 정도 증가하였다. 본 실험에서 얻은 결과는 향후 저전압 DRAM 개발과 응용에 상당한 기여를 할 것으로 기대된다.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.1
• /
• pp.93-98
• /
• 2013

In this paper, We have fabricated PMMA thin films by plasma polymerization method for organic thin film transistor's insulator layer. For improving the characteristics of organic transistor, we tested transistor's mobility and output values with organic transistor's electrode structures. As a results, the mobility of top contact was $8{\times}10^{-3}[cm^2V^{-1}s^{-1}]$, that of bottom contact was $2{\times}10^{-4}[cm^2V^{-1}s^{-1}]$. Also, off current of bottom contact was increased. Therefore, we recommend the top contact electrode structure of organic transistor.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.6
• /
• pp.797-803
• /
• 2013

In this paper, we fabricated insulator thin films by plasma polymerization method for organic thin film transistor's insulator layer. For improving the electrical characteristics of organic transistor, we treated the semiconductor thin film with $O_2$ plasma. As results, the surface energy of organic transistor was increased from $38mJ/m^2$ to $72mJ/m^2$ and the mobility of organic transistor was increased $0.057cm^2V^{-1}s^{-1}$, that is increased 29% average ratio. Therefore, we have known that oragnic transistor's mobility can improve with plasma treatment of semiconductor thin film's surface.

• The KIPS Transactions:PartA
• /
• v.15A no.2
• /
• pp.69-74
• /
• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.307-309
• /
• 2009

We have fabricated vertical-type organic transistors (static induction transistors; SITs) with built-in nano-triode arrays formed in parallel by a colloidal-lithography technique. Using this technique, we could fabricate a microstructure in a lateral direction within a large-scale organic device without relying on photolithography. The organic transistor showed low operating voltages, high current output, and large transconductance.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.294.1-294.1
• /
• 2016

Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3. The doping level is controlled in the non-degenerate regime, where performance parameters of PPh3 doped WSe2 transistor can be optimized.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.8
• /
• pp.1290-1298
• /
• 1989

A new dynamic RAM cell called Trench Epitaxial Transistor Cell (TETC) has been developed for 4M to 16M DRAMS. Also the fabrication process for device isolation which can decrease the narrow effect using SEG process has been developed. We verified the characteristic of the new cell structure with the PICSES simulator on VAX8450.