• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.185-195
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• 2009

As most systems get more complicated, system analysis using simulation has been taken notice of. One of the core parts of simulation analysis is validation of a simulation model, and we can identify how well the simulation model represents the real system with this validation process. The difference between input data of two systems has an effect on the comparison between a simulation model and a real system at validation stage, and the result with such difference is not enough to ensure high credibility of the model. Accordingly, in this paper, we construct a model based on Trace-driven simulation which uses identical input data with the real system. On the other hand, to validate a model by each class, not by an unique statistic, we validate the model using a metric transformed from F-measure which estimates performance of a classifier in data mining field. Finally, this procedure enables precise validation process of a model, and it helps modification by offering feedback at the validation phase.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.6
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• pp.849-861
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• 1995

In this paper, a new trace driven simulation algorithm is proposed to evaluate the bus traffic and the miss ration of the various sector cache memories, which have various sub-block sizes and block sizes and associativities and number of sets, with a single pass through an address trace. Trace-driven simulaton is usually used as a method for performance evaluation of sector cache memories, but it spends a lot of simulation time for simulating the diverse cache configurations with a long address trace. The proposed algorithm shortens the simulation time by evaluating the performance of the various sector cache configurations. which have various sub-block sizes and block sizes and associativities and number of sets , with a single pass through an address trace. Our simulation results show that the run times of the proposed simulation algorithm can be considerably reduced than those of existing simulation algorithms, when the proposed algorithm is miplemented in C language and the address traces obtained from the various sample programs are used as a input of trace-driven simulation.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.983-991
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• 1996

This paper proposes an improved write-piggybacking technique called hybrid write-piggybacking, and evaluates its performance. The performance of the proposed hybrid write-piggybacking technique is done through a trace-driven simulation using a model of a real disk system. The results of simulation show that the proposed hybrid write-piggybacking has better performance compared to the original write-piggybacking technique.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.35-44
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• 2003

The effectiveness of buffer cache replacement algorithms is critical to the performance of I/O systems. In this paper, we propose the degree of inter-reference gap (DIG) based block replacement scheme that retains merits of the least recently used (LRU) such as simple implementation and good cache hit ratio (CHR) for general patterns of references, and improves CHR further. In the proposed scheme, cache blocks with low DIGs are distinguished from blocks with high DIGs and the replacement block is selected among high DIGs blocks as done in the low inter-reference recency set (LIRS) scheme. Thus, by having the effect of the partitioning the cache memory dynamically based on DIGs, CHR is improved. Trace-driven simulation is employed to verified the superiority of the DIG based scheme and shows that the performance improves up to about 175% compared to the LRU scheme and 3% compared to the LIRS scheme for the same traces.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.7
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• pp.429-439
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• 2006

A desktop grid, which is a computing grid composed of idle computing resources in a large network of desktop computers, is a promising platform for compute-intensive distributed computing applications. However, due to reliability and unpredictability of computing resources, effective scheduling of parallel computing applications on such a platform is a difficult problem. This paper proposes a new scheduling method aimed at reducing the total execution time of a parallel application on a desktop grid. The proposed method is based on utilizing the histories of execution behavior of individual computing nodes in the scheduling algorithm. In order to test out the feasibility of this idea, execution trace data were collected from a set of 40 desktop workstations over a period of seven weeks. Then, based on this data, the execution of several representative parallel applications were simulated using trace-driven simulation. The simulation results showed that the proposed method improves the execution time of the target applications significantly when compared to previous desktop grid scheduling methods. In addition, there were fewer instances of application suspension and failure.

• Journal of Korea Game Society
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• v.6 no.4
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• pp.63-70
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• 2006

This paper studied various low power structures of texture caches for mobile 3D graphics accelerator to reduce the memory latency of texture data. Also the paper designed the texture cache with the variable threshold values of power mode transition according to the filtering algorithms. In the trace driven simulation, we compared the performance of those structures using Quake game engine as the benchmark. Also the algorithm was proposed and verified by the simulation, which has variable threshold values of power mode transitions according to the selected texture filtering method.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.05a
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• pp.1179-1185
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• 2003

시뮬레이션 상의 입력모델에 대한 기존의 연구는 과거의 자료를 바탕으로 선형의 모수적인 (parametric) 모형을 개발하는데 초점을 두고 있다. 그러나 이 경우에는 입력이 매우 복잡한 형태를 가지면 모수적인 모형을 잦는 것이 불가능해지므로 비모수적인(non-parametric) 접근방법이 절실한 실정이다 예로 인터넷 트래픽 모델의 시뮬레이션 수행시 입력으로 제공되는 단위 시간당 요구되는 웹 페이지의 수 같은 경우 데이터들 간데 종속관계가 매우 심하고 복잡하여 모수적 모형을 세우는데 어려움이 있다. 이러한 시스템들을 시뮬레이션 방법으로 분석 하고자 할 때, 기존의 trace-driven 시뮬레이션 방법이나 모수적 모형을 찾아 다수의 사실적인 시뮬레이션 입력 자료를 확보하는 것은 현실적으로 어려움이 있다. 따라서. 비모수적인 방법으로 다수의 사실적인 시뮬레이션 입력 자료를 생성하는 것이 필요하다. 이러한 비모수적인 방법에 대한 평가기준 설정은 시뮬레이션 상의 입력 모델에 대한 타당성을 제시한다는 점에서 또한 매우 중요하다. 본 논문에서는 붓트스트 랩의 방법중의 하나인 임계값 붓트스트랩을 이용하여 시뮬레이션 입력 자료 생성 방법을 개발하였고 Turing test를 통해 붓스트랩으로 생성산 입력 시나리오를 검증하였다.

• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2676-2685
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• 1998

In order to improve the branch prediction accuracy and to reduce the BTB miss rate, this paper proposes a two-level BTB structure that adds small-sized victim BTB to the convetional BTB. With small cost, two-level BTB can reduce the BTB miss rate as well as improve the prediction accuracy of the hybrid branch prediction strategy which combines dynamic prediction and static prediction. Through the trace-driven simulation of four bechmark programs, the performance improvement by the proposed two-level BTB structure is analysed and validated. Our proposed BTB structure can improve the BTB miss rate by 26.5% and the misprediction rate by 26.75%

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1652-1659
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• 1998

To provide performance gains by reducing the operand referencing latency and data cache bandwidth requirements, we present an operand reference prediction cache (ORPC) which predicts operand value and address translation during the instruction fetch stage. The prediction is verified in the early stage, and thus it minimizes the performance penalty caused by the misprediction. Through the trace-driven simulation of six benchmark programs, the performance improvement by proposed three aRPC stmctures (OfiPC1, OfiPC2. ORPC3)is analysed and validated.

• ETRI Journal
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• v.9 no.1
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• pp.37-42
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• 1987

개인용 전자자동설계 시스팀인 EDAS_P의 schematic으로부터 직접 디지틀 회로의 논리동작을 시뮬레이션할 수 있는 게이트 레벨 논리 시뮬레이터(GLSIM_P)를 IBM PC에서 C언어를 이용하여 개발하였다. 다룰수 있는 소자로는 input clock, 일반 게이트 및 clocked 게이트, ROM, RAM, PLA등이다. 논리신호 레벨은 1, 0,*(intermediate)이다. 효율적인 논리해석을 위해 selective trace 및 event driven 방식을 도입하였으며 게이트 500개 정도까지 해석이 가능하다.