• Title/Summary/Keyword: Toffoli 게이트

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Realization of Multiple-Control Toffoli gate based on Mutiple-Valued Quantum Logic (다치양자논리에 의한 다중제어 Toffoli 게이트의 실현)

  • Park, Dong-Young
    • Journal of Advanced Navigation Technology
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    • v.16 no.1
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    • pp.62-69
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    • 2012
  • Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

Trends in Toffoli gate decomposition (Toffoli gate 분해에 대한 동향)

  • Hyun-Jun Kim;Se-Jin Lim;Hwa-Jeong Seo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2023.05a
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    • pp.165-167
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    • 2023
  • 양자 컴퓨터는 기존의 클래식 컴퓨터와 달리 양자역학 원리를 활용해 정보 처리를 수행하며, 특정 문제들을 훨씬 빠르게 해결할 수 있다. 양자 컴퓨터는 큐빗을 기본 단위로 사용하고, 아다마르 게이트, CNOT 게이트, 파울리 게이트, 토플리 게이트 등을 조합하여 양자 회로를 구성한다. Toffoli 게이트는 유니버설 게이트 중 하나로, 세 개의 큐빗을 입력받아 조건부 (Controlled-Controlled) NOT 연산을 수행한다. 이 게이트는 복잡한 작업을 기본 양자 게이트로 분해할 수 있어, 회로의 게이트 수, 깊이 및 오류율 측면에서 최적화할 수 있다. 기본 양자 게이트 중 T 게이트는 노이즈와 오류에 영향을 받을 수 있으므로, T 게이트의 수와 깊이를 최적화하는 것이 중요하다. 본 논문은 Toffoli 게이트 분해를 통해 양자 회로의 게이트 수와 깊이를 최적화하는 방법을 조사한다.

Gate Cost Reduction Policy for Direct Irreversible-to-Reversible Mapping Method without Reversible Embedding (가역 임베딩 없는 직접적 비가역-가역회로 매핑 방법의 게이트비용 절감 방안)

  • Park, Dong-Young;Jeong, Yeon-Man
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.11
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    • pp.1233-1240
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    • 2014
  • For the last three decades after the advent of the Toffoli gate in 1980, while many reversible circuit syntheses have been presented reversible embedding methods onto suitable reversible functions, only a few proposed direct irreversible-to-reversible mapping methods without reversible embedding. In this paper we present two effective policies to reduce the gate cost and complexity for the existing direct reversible mapping methods without reversible embedding. In order to develop new cost reduction policies we consider the cost influence of Toffoli module according to NOT gate arrangement in classical circuits. From this we deduced an inverse proportional property between inverting input numbers of classical AND/OR gates and reversible Toffoli module cost based on a fact - the inverting inputs of classical AND(OR) gates increase(decrease) the Toffoli module cost. We confirm the applications of the inverting input rearrangement and maximum fan-out policies preceding direct reversible mapping will be effective method to improve the reversible Toffoli module cost and complexity with the parallel using of the fan-out and supercell ones.

Augmented Quantum Short-Block Code with Single Bit-Flip Error Correction (단일 비트플립 오류정정 기능을 갖는 증강된 Quantum Short-Block Code)

  • Park, Dong-Young;Suh, Sang-Min;Kim, Baek-Ki
    • The Journal of the Korea institute of electronic communication sciences
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    • v.17 no.1
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    • pp.31-40
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    • 2022
  • This paper proposes an augmented QSBC(Quantum Short-Block Code) that preserves the function of the existing QSBC and adds a single bit-flip error correction function due to Pauli X and Y errors. The augmented QSBC provides the diagnosis and automatic correction of a single Pauli X error by inserting additional auxiliary qubits and Toffoli gates as many as the number of information words into the existing QSBC. In this paper, the general expansion method of the augmented QSBC using seed vector and the realization method of the Toffoli gate of the single bit-flip error automatic correction function reflecting the scalability are also presented. The augmented QSBC proposed in this paper has a trade-off with a coding rate of at least 1/3 and at most 1/2 due to the insertion of auxiliary qubits.