• Title/Summary/Keyword: Timing Error Detector

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A New Frame Synchronization Scheme for Underwater Ultrasonic Image Burst Transmission System (초음파를 이용한 수중 영상 버스트 전송 시스템을 위한 새로운 프레임 동기 방안)

  • Kim, Seung-Geun;Choi, Young-Chol;Park, Jong-Won;Kim, Sea-Moon;Lim, Yong-Gon;Kim, Sang-Tae
    • Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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    • 2003.05a
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    • pp.336-340
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    • 2003
  • The frame synchronization should be acquired before performing other data-aided receiving algorithms, such as data-aided channel equalizing, beam-forming and phase, symbol timing, and frequency synchronizing, since all of them are using preamble or training sequence to estimate the amount of error from the received signal. In this paper, we present a new frame synchronization scheme for underwater ultrasonic image burst transmission system, which computes the correlation between received symbol sequence and one CAZAC sequence, composed of the latter half of the first CAZAC sequence of preamble and the first half of the second CAZAC sequence of preamble and then compares a threshold value. If the correlation value is bigger than the threshold value, the frame detector determines that the frame synchronization is achieved at that sample.

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Design of Digital PLL with Asymmetry Compensator in High Speed DVD Systems (고속 DVD 시스템에서 비대칭 신호 보정기와 결합한 Digital PLL 설계)

  • 김판수;고석준;최형진;이정현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12A
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    • pp.2000-2011
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    • 2001
  • In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

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