• Title/Summary/Keyword: Timing Error

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Sea Trial Results of the Direct Sequence Spread Spectrum Underwater Acoustic Communication in the East Sea (동해에서 직접 수열 대역확산 수중음향통신 기법의 해상실험 결과)

  • Han, Jeong-Woo;Kim, Ki-Man;Yun, Yeong-Jung;Mun, Hyeon-Uk;Chun, Seung-Yong;Son, Kweon
    • The Journal of the Acoustical Society of Korea
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    • v.31 no.7
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    • pp.441-448
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    • 2012
  • Spread spectrum provides the minimized inter-symbol interference, the low probability of intercept and the multiple access capability. This paper presents a direct sequence spread spectrum with carrier/timing recovery and equalizer which compensates the delay spread caused by multipath transmission. When the sea trials were performed in Korean East Sea, the bit error rates of QPSK and direct sequence spread spectrum are $1.46{\times}10^{-2}$ and $5.17{\times}10^{-4}$ at 3 km source-receiver range, respectively.

A Study on the Preprocessing Method Using Construction of Watershed for Character Image segmentation

  • Nam Sang Yep;Choi Young Kyoo;Kwon Yun Jung;Lee Sung Chang
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.814-818
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    • 2004
  • Off-line handwritten character recognition is in difficulty of incomplete preprocessing because it has not dynamic and timing information besides has various handwriting, extreme overlap of the consonant and vowel and many error image of stroke. Consequently off-line handwritten character recognition needs to study about preprocessing of various methods such as binarization and thinning. This paper considers running time of watershed algorithm and the quality of resulting image as preprocessing For off-line handwritten Korean character recognition. So it proposes application of effective watershed algorithm for segmentation of character region and background region in gray level character image and segmentation function for binarization image and segmentation function for binarization by extracted watershed image. Besides it proposes thinning methods which effectively extracts skeleton through conditional test mask considering running time and quality. of skeleton, estimates efficiency of existing methods and this paper's methods as running time and quality. Watershed image conversion uses prewitt operator for gradient image conversion, extracts local minima considering 8-neighborhood pixel. And methods by using difference of mean value is used in region merging step, Converted watershed image by means of this methods separates effectively character region and background region applying to segmentation function. Average execution time on the previous method was 2.16 second and on this paper method was 1.72 second. We prove that this paper's method removed noise effectively with overlap stroke as compared with the previous method.

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Performance Evaluation of a Pilot Interference Cancellation Scheme in a WCDMA Wireless Repeater (WCDMA 무선 중계기에서 파일럿 간섭제거 기법의 성능평가)

  • Kim, Sun-Ho;Shim, Hee-Sung;Im, Sung-Bin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.6
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    • pp.111-117
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    • 2009
  • In the wideband code division access (WCDMA) systems, a pilot channel is used to determine WCDMA network coverage, cell identification, synchronization, timing acquisition and tracking, user-set handoff, channel estimation, and so on. A wireless repeater, which is deployed in the urban area for the WCDMA system to meet the growing demand on wireless communication services, has the possibility to receive several pilot signals from a large number of base stations, however, cannot distinguish its service base station's signal among them. This pilot interference results in frequent handoffs in the user equipment, which degrades the radio reception, transmission efficiency, quality of service, and channel capacity and increases the unwanted power consumption. In this paper, thus, we propose a pilot pollution interference cancellation scheme using one of the adaptive estimation algorithms, normalized least mean square (NLMS), which is applicable to a wireless repeater. We carried out link-level and network-level computer simulations to evaluate the performance of the proposed scheme in a wireless repeater. The simulation results verify the bit error rate (BER) improvement in the link level and the call drop probability improvement in the network level.

Effect of Synchronization Errors with Distributed Beamforming in OFDM Systems (분산 빔포밍을 이용한 OFDM 시스템에서의 동기에러 영향 분석)

  • Kim, Haesoo;Lee, Kwangho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.1
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    • pp.3-10
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    • 2014
  • Three synchronization issues, i.e., symbol time, phase, and frequency, have to be properly controlled to achieve distributed beamforming gain. In this paper, the impacts of synchronization errors in distributed beamforming are analyzed for OFDM systems. For symbol timing error of cooperating signals, high frequency subcarriers are more susceptible as compared to low frequency ones. The desired signal loss due to phase and frequency offset is independent of subcarrier number. However, frequency offset is critical in OFDM systems since it leads to interference from the other subcarriers as well as power loss in the desired signal. Performance degradation due to three synchronization errors is shown with various numbers of cooperating signals and offset values. It shows that the performance analysis is well matched with simulation results.

Validation of diesel engine gas flow one-dimensional numerical analysis using the method of characteristics (특성곡선법을 이용한 디젤엔진 가스유동 1차원 수치해석의 타당성 평가)

  • KIM, Kyong-Hyon;KONG, Kyeong-Ju
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.56 no.3
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    • pp.230-237
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    • 2020
  • In order to design a diesel engine system and predict its performance, it is necessary to analyze the gas flow of the intake and exhaust system. A gas flow analysis in three-dimensional (3D) format needs a high-resolution workstation and enormous time for analysis. Therefore, the method of characteristics (MOC) was used for a gas flow analysis with a fast calculation time and a low-resolution workstation. An experiment was conducted on a single cylinder diesel engine to measure pressure in cylinder, intake pipe and exhaust pipe. The one-dimensional (1D) gas flow was analyzed under the same conditions as the experiment. The engine speed, valve timing and compression ratio were the same conditions and the intake pressure was inputted as the experimental results. Bent pipe such as an exhaust port that cannot be realized in 1D was omitted. As results of validation, the cylinder pressure showed accuracy, but the exhaust pipe pressure exhibited inaccuracy. This is considered as an error caused by the failure to implement a bent pipe such as an exhaust port. When analyzed in 3D, calculation time required 61 hours more based on a model of this study. In the future, we intend to implement a bent pipe that cannot be realized in 1D using 3D and prepare a method to supplement reliability by using 1D-3D coupling.

Production Data Analysis to Predict Production Performance of Horizontal Well in a Hydraulically Fractured CBM Reservoir (수압파쇄된 CBM 저류층에서 수평정의 생산 거동예측을 위한 생산자료 분석)

  • Kim, Young-Min;Park, Jin-Young;Han, Jeong-Min;Lee, Jeong-Hwan
    • Journal of the Korean Institute of Gas
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    • v.20 no.3
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    • pp.1-11
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    • 2016
  • Production data from hydraulically fractured well in coalbed methane (CBM) reservoirs was analyzed using decl ine curve analysis (DCA), flow regime analysis, and flowing material balance to forecast the production performance and to determine estimated ultimate recovery (EUR) and timing for applying the DCA. To generate synthetic production data, reservoir models were built based on the CBM propertie of the Appalachian Basin, USA. Production data analysis shows that the transient flow (TF) occurs for 6~16 years and then the boundary dominated flow (BDF) was reached. In the TF period, it is impossible to forecast the production performance due to the significant errors between predicted data and synthetic data. The prediction can be conducted using the production data of more than a year after reached BDF with EUR error of approximately 5%.

Design of a High-speed Decision Feedback Equalizer using the Constant-Modulus Algorithm (CMA 알고리즘을 이용한 고속 DFE 등화기 설계)

  • Jeon, Yeong-Seop;;Kim, Gyeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.4
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    • pp.173-179
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    • 2002
  • This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

Envelope Elimination and Restoration Transmitter for Efficiency and Linearity Improvement of Power Amplifier (전력증폭기의 효율 및 선형성 개선을 위한 포락선 제거 및 복원 송신기)

  • Cho, Young-Kyun;Kim, Changwan;Park, Bong Hyuk
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.3
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    • pp.292-299
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    • 2015
  • An envelope elimination and restoration transmitter that uses a tri-level envelope encoding scheme is presented for improving the efficiency and linearity of the system. The proposed structure amplifies the same magnitude signal regardless of the input peak-to-average power ratio and reduces the quantization noise by spreading out the noise to the out-of-band frequency, resulting in the enhancement of power efficiency. An improved linearity is also obtained by providing a new timing mismatch calibration technique between the envelope and phase signal. Implementation in a 130 nm CMOS process, transmitter measurements on a 20-MHz long-term evolution input signal show an error vector magnitude of 3.7 % and an adjacent channel leakage ratio of 37.5 dBc at 2.13 GHz carrier frequency.

Design of ${\gamma}$=1/3, K=9 Convolutional Codec Using Viterbi Algorithm (비터비 알고리즘을 이용한 r=1/3, K=9 콘벌루션 복부호기의 설계)

  • 송문규;원희선;박주연
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7B
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    • pp.1393-1399
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    • 1999
  • In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

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Automatic Virtual Platform Generation for Fast SoC Verification (고속 SoC 검증을 위한 자동 가상 플랫폼 생성)

  • Jung, Jun-Mo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.9 no.5
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    • pp.1139-1144
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    • 2008
  • In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform