• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.305-307
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• 2009

When we design the control system used Programmable Logic Controller(PLC), we program the main algorithm by Ladder Diagram(LD) among the standard language. We can substitute the select sequence function by the unique sequence. We can implement this function by the delay time. Therefore this thesis show the select sequence function by the unique sequence and we confirmed its feasibility through actual example.

• 한국CDE학회논문집
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• 제6권4호
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• pp.244-253
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• 2001

For more complete process planning, machining sequence determination is critical to attain machining economics. Although many studies have been conducted in recent years, most of them suggests the non-unique machining sequences. When the tool approach directions(TAD) are considered fur a feature, both machining time and number of setups can be reduced. Then, the unique machining sequence can be extracted from alternate(non-unique) sequences by minimizing the idle time between operations within a sequence. This study develops an algorithm to generate the best machining sequence for composite prismatic features in a vertical milling operation. The algorithm contains five steps to produce an unique sequence: a precedence relation matrix(PRM) development, tool approach direction determination, machining time calculation, alternate machining sequence generation, and finally, best machining sequence generation with idle times. As a result, the study shows that the algorithm is effective for a given composite feature and can be applicable fur other prismatic parts.

• 한국통신학회논문지
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• 제19권5호
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• pp.952-958
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• 1994

본 논문에서 정수론에 기초한 이진수호와 이전된 이진부호 사이의 시간옵셉을 계산하는 방법을 제시한다. 이 방법을 이용하여 이진부호 사이의 시간옵셉을 계산할 수 있다. 모든 기지국은 동일한 확산부호를 사용하므로써 동기 부호분할 다원접속 시스템에서 기준(영 \ulcorner\ulcornerV)부호를 정의하는 것은 중요하다. 다른 기지국으로부터 이동국에 수신되는 신호를 구별하기 위하여 영옵셉부호에 대한 시간옵셉을 사용하고 있다. 본 논문은 기준부호를 정의하는 방법을 제시한다.

• 한국통신학회논문지
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• 제13권5호
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• pp.422-428
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• 1988

반복 학습제어시스템은 시행을 반복함으로써 유한시간의 목표출력에 대하여 추종해 가도록 하는 것이다. 본 논문에서는 이산시간 시스템에 있어서의 이산 시간 학습제어 입력을 구하는 방법을 제안한다. 여기서 현재시행의 제어입력은 바로 전시행에서 입력 sequence와 time-shift된 error sequence의 선형조합에 의하여 구해진다. 컴퓨터로 제어되는 이산시간 시스템에서 error신호의 미분조작이 필요한 연속시간 Betterment Process에 비하여 error sequence의 time-shift조작은 보다 간단해지며 컴퓨터 시뮬레이션을 통하여 그 유효성을 확인하였다.

• 한국정보과학회논문지:데이타베이스
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• 제30권4호
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• pp.372-380
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• 2003

시간에 따라 변화하는 사건들을 저장하는 시간지원 데이타베이스에서 기존의 집계 처리 기법에 시간을 고려하여 처리하도록 확장해야 한다. 기존의 시간지원 집계 처리 기법들은 매번 질의의 대상이 되는 사건들이 다를 때마다 시간 구간을 반복해서 구하고 그 구간마다의 결과를 계산해야 한다는 문제점이 있다. 본 논문에서는 시간지원 데이타베이스에 저장된 사건의 시작 시간과 종료 시간만을 미리 읽어 들여서 구성한 시점 시퀀스를 이용하여 시간지원 집계를 처리하는 방법을 제안하였다. 또한 데이타베이스에서 저장된 사건의 삭제나 새로운 사건의 삽입에 따른 시점 시퀀스 갱신의 용이성에 대해서도 언급하였다. 시점 시퀀스는 시간 구간에 대한 정보를 미리 저장하고 있기 때문에, 질의의 대상이 되는 사건들이 다른 시간지원 집계 질의가 계속해서 들어올 때 기존의 방법에 비해 효율적으로 처리할 수 있다.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 산업경영시스템학회지
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• 제43권3호
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• pp.10-20
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• 2020

This paper presents a method to measure the similarity of assigned jobs in the gravure printing operation based on the chromaticity and color sequence, and order the jobs accordingly. The proposed dispatching rule can be used to fulfill diverse manufacturing site requirements because the parameters can be adjusted to prioritize chromaticity and color sequence. In general, dispatching rules either ignore the job-changing time or require that the time be clearly defined. However, in the gravure printing operation targeted in this study, it is difficult to apply the general dispatching rule because of the difficulties in quantifying the job-changing time. Therefore, we propose a method for generalizing assignment rules of the job planner, allocating relative similarity among assigned jobs, and determining the sequence of jobs accordingly. Chromaticity priority is determined by the arrangement of the color assignments in the printing operation; color sequence priority is determined by the addition, deletion, or change in a specific color sequence. Finally, the job similarity is determined by the dot product of the chromaticity and color sequence priorities. Implementation of the proposed dispatching rule at an actual manufacturing site showed the planner present the same job order as that obtained using the proposed rule. Therefore, this rule is expected to be useful in industrial sites where clear quantification of the job-changing time is not possible.

• Journal of Welding and Joining
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• 제27권2호
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• pp.57-62
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• 2009

This research was carried out to improve the productivity in the subassembly process of shipbuilding through optimal work planning for the shortest work time. The work time consist of welding time, moving time of gantry, teaching time of robot and robot motion time. The shortest work time is accomplished by even distribution of work and the shortest welding sequence. Even distribution of work was done by appling the simple algorithm. The shortest work sequence was determined by using GA. The optimal work planning decreased the total work time of the subassembly process by 4.1%. The result showed the effectiveness of the suggested simple algorithm for even distribution of work and GA for the shortest welding sequence.

• 한국자기공명학회논문지
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• 제1권1호
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• pp.7-20
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• 1997

The mapping of the spin-spin relaxation time T2 in pixed-by-pixel was suggested as a quantitative diagnostic tool in medicine. Although the CPMG pulse sequence has been known to be the best pulse sequence for T2 measurement in physics NMR, the supplied pulse sequence by the manufacture of MRI system was able to obtain the maximum of 4 CPMG images. Eight or more images with different echo time TEs are required to construct a reliable T2 map, so that two or more acquisitions were required, which easily took more than 10 minutes. 4-echo CPMG imaging pulse sequence was modified to generate the maximum of 8 MR images with evenly spaced echo time TEs. In human MR imaging, since patients tend to move at least several pixels between the different acquisitions, 8-echo CPMG imaging sequence reduces the acquisition time and may remove any misregistration of each pixel's signal for the fitting T2. The resultant T2 maps using the theoretically simulated images and using the MR images of the human brain suggested that 8 echo CPMG sequence with short echo spacing such as 17∼20 msec can give the reliable T2 map.

• 한국컴퓨터정보학회논문지
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• 제21권3호
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• pp.57-64
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• 2016

This paper deals with the PCB assembly time minimization problem that the PAP (pick-and-placement) machine pickup the K-weighted group of N-components, loading, and place into the PCB placement location. This problem considers the rotational turret velocity according to component weight group and moving velocity of distance in two component placement locations in PCB. This paper suggest heavy-weight component group first pick-and-place strategy that the feeder sequence fit to the placement location Hamiltonean cycle sequence. This algorithm applies the quadratic assignment problem (QAP) that considers feeder sequence and location sequence, and the linear assignment problem (LAP) that considers only feeder sequence. The proposed algorithm shorten the assembly time than iATMA for QAP, and same result as iATMA that shorten the assembly time than ATMA.