• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.1
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• pp.153-166
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• 2011

Recent trends in mobile device market whose services are rapidly expanding to provide wireless internet access are drawing people's attention to mobile security. Especially, since threats to information leakage are reaching to the critical level due to the frequent interchange of important data such as personal and financial information through wireless internet, various encryption algorithms has been developed to protect them. The encryption algorithms confront the serious threats by the appearance of side channel attack (SCA) which uses the physical leakage information such as timing, and power consumption, though the their robustness to threats is theoretically verified. Against the threats of SCA, researches including the performance and development direction of SCA should precede. Among tile SCA methods, the power analysis (PA) attack overcome this misalignment problem. The conventional methods require large computational power and they do not effectively deal with the delay changes in a power trace. To overcome the limitation of the conventional methods, we proposed a novel alignment method using peak matching. By computer simulations, we show the advantages of the proposed method compared to the conventional alignment methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.1000-1010
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• 2006

This paper proposes a new architecture for DCT-based motion estimation and compensation. Previous methods do riot take sufficient advantage of the sparseness of 2-D DCT coefficients to reduce execution time. We first derive a recursion equation to perform DCT domain motion estimation more efficiently; we then use it to develop a wavefront array processor (WAP) consisting of processing elements. In addition, we show that the recursion equation enables motion predicted images with different frequency bands, for example, from the images with low frequency components to the images with low and high frequency components. The wavefront way Processor can reconfigure to different motion estimation algorithms, such as logarithmic search and three step search, without architectural modifications. These properties can be effectively used to reduce the energy required for video encoding and decoding. The proposed WAP architecture achieves a significant reduction in computational complexity and processing time. It is also shown that the motion estimation algorithm in the transform domain using SAD (Sum of Absolute Differences) matching criterion maximizes PSNR and the compression ratio for the practical video coding applications when compared to tile motion estimation algorithm in the spatial domain using either SAD or SSD.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.10
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• pp.1005-1016
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• 2002

In this paper, a 2 GHz tapered shape of multiport power divider/combiner modified from the model published by [10] and adopted PBG(Photonic Band Gap) structure is proposed. Parameters determining electrical property of the circuit structure have been analyzed by HFSS simulation. For input matching, balance of output signals and phase linearity at each output port, one circular hole has been etched out on the circuit surface. 1:2 and 1:3 power dividers/combiners designed by this study have been compared with the same circuits designed by the method of [10] in terms of S-parameters. As a result, it has been found that tile modified structure and PBG of power divider/combiner have improved return loss more than 20 dB and another 18 dB. respectively, at 2 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.754-763
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• 2002

This paper discusses the improved power performances of the size-reduced amplifier using defected ground structure (DGS). The slow-wave effect and enlarged electrical length occur due to the additional equivalent circuit elements of DGS. Using these properties, it is possible to reduce the length of transmission lines in order to keep the same original electrical lengths by inserting DGS on the ground plane. The matching and performances of the amplifier are preserved even after DGS patterns have been inserted. While there is no loss in the size-reduced transmission lines at the operating frequency, but there exists loss to some extent at harmonic frequencies. This leads to the more excellent inherent capability of harmonic rejection of the size-reduced amplifier. Therefore, it is expected tile harmonics of the size-reduced amplifier are smaller than those of the original amplifier. The measured second harmonic, third order intermodulation distortion (IMD3), and adjacent channel power ratio (ACPR) of the size-reduced amplifier are smaller than those of the original amplifier by 5 dB, 2~6 dB, and 1~4 dB, respectively, as expectation.