• 전력전자학회논문지
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• 제19권2호
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• pp.173-183
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• 2014

In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.75-76
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• 2012

This paper presents an analysis of power losses in three-level T-Type Inverters. The switching loss in different switching frequencies and the conduction loss at different modulation indices and power factors are investigated. Finally, it is shown that the results of analysis coincide with those which resulted from CASPOC software simulation.

• Journal of Power Electronics
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• 제14권6호
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• pp.1197-1207
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• 2014

Common-mode voltage (CMV) causes overvoltage stress to winding insulation and damages AC motors. CMV with high dv/dt causes leakage currents, which create noise problems for equipment installed near the converter. This study proposes a new pulse-width modulation (PWM) strategy for three-level T-type NPC inverters. This strategy substantially eliminates CMV. The principle for selecting suitable triangle carrier signals for the three-level T-type NPC is described. The proposed method can mitigate the peak value of CMV by 50% compared with the phase disposition pulse-width modulation method. Furthermore, the proposed method exhibits better harmonic spectrum and lower root mean square value for the CMV than those of the reduced-CMV method on the basis of the phase opposition disposition PWM scheme with modulation index higher than 0.5. The proposed modulation can easily be implemented using software without any additional hardware modifications. Both simulation and experimental results demonstrate that the proposed carrier phase-shift PWM method has good output waveform performance and reduces CMV.

• Journal of Power Electronics
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• 제18권5호
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• pp.1458-1469
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• 2018

This paper proposes a novel common-mode voltage (CMV) elimination (CMV-EL) method based on model predictive control (MPC) to eliminate CMV for three-level T-type inverters (3LT2Is). In the proposed MPC method, only six medium and one zero voltage vectors (VVs) (6MV1Z) that generate zero CMV are considered as candidates to perform the MPC. Moreover, the influence of dead-time effects on the CMV of the MPC-based 6MV1Z method is investigated, and the candidate VVs are redesigned by pre-excluding the VVs that will cause CMV fluctuations during the dead time from 6MV1Z. Only three or five VVs are included to perform optimization in every control period, which can significantly reduce the computational complexity. Thus, a small control period can be implemented in the practical applications to achieve improved grid current performance. With the proposed CMV-EL method, the CMV of the $3LT^2Is$ can be effectively eliminated. In addition, the proposed CMV-EL method can balance the neutral point potentials (NPPs) and yield satisfactory performance for grid current tracking in steady and dynamic states. Simulation and experimental results are presented to verify the effectiveness of the proposed method.

• Journal of Electrical Engineering and Technology
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• 제12권6호
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• pp.2227-2236
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• 2017

In order to solve the neutral-point voltage fluctuation problem of three-phase three-level T-type inverters (TPTLTIs), the unbalance characteristics of capacitor voltages under different switching states and the mechanism of neutral-point voltage fluctuation are revealed. Based on the mathematical model of a TPTLTI, a feed-forward voltage balancing control strategy of DC-link capacitor voltages error is proposed. The strategy generates a DC bias voltage using a capacitor voltage loop with a proportional integral (PI) controller. The proposed strategy can suppress the neutral-point voltage fluctuation effectively and improve the quality of output currents. The correctness of the theoretical analysis is verified through simulations. An experimental prototype of a TPTLTI based on Digital Signal Processor (DSP) is built. The feasibility and effectiveness of the proposed strategy is verified through experiment. The results from simulations and experiment match very well.