• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1220-1224
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• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.83-87
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• 2002

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride ($SiN_X$) is widely used as a gate dielectric material for the hydrogenated amorphous silicon(a-Si:H) thin film transistors (TFT's). We investigated $SiN_X$ films were deposited PECVD at low temperature ($300^{\circ}C$). The reaction gases were used pure nitrogen and a helium diluted of silane gas(20% $SiH_4$, 80% He). Experimental investigations were carried out with the variation of $N_2/SiH_4$ flow ratios from 3 to 50 and the rf power of 200 W. This article presents the $SiN_X$ gate dielectric studies in terms of deposition rate, hydrogen content, etch rate and C-V, leakage current density characteristics for the gate dielectric layer of thin film transistor applications. Electrical properties were analyzed through high frequency (1MHz) C-V and current-voltage (I-V) measurements. The thickness and the refractive index on the films were measured by ellipsometry and chemical bonds were determined by using an FT-IR equipment.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.286-286
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• 2011

최근 폴리머를 기판으로 하는 Flexible TFT (thin film transistor)나 3D-ULSI (three dimensional ultra large-scale integrated circuit)에서 높은 에너지 소비효율과, 빠른 반응 속도를 실현 시키기 위해 낮은 비저항(resistivity)을 가지며, 높은 홀 속도(carrier hall mobility)를 가지는 다결정 반도체 박막(poly-crystalline thin film)을 만들고자 하고 있다. 이를 실현 시키기 위해서는 높은 온도에서 장시간의 열처리가 필요하며, 이는 폴리머 기판의 문제점을 야기시킬 뿐 아니라 공정시간이 길다는 단점이 있었다. 이에 반도체 박막의 재결정화 온도를 낮춰주는 metal (Al, Ni, Co, Cu, Ag, Pd etc.,)을 이용하여 결정화 시키는 방법이 많이 연구 되어지고 있지만, 이 또한 재결정화가 이루어진 반도체 박막 안에 잔여 금속(residual metal)이 존재하게 되어 비저항을 높이고, 홀 속도를 감소시키는 단점이 있다. 이에 본 실험은 HiPIMS (High power impulse magnetron sputtering)와 PIII and D (plasma immersion ion implantation and deposition) 공정을 복합시킨 프로세스로 적은양의 금속이온주입을 통하여 재결정화 온도를 낮췄을 뿐 아니라, 잔여 하는 금속의 양도 매우 적은 다결정 반도체 박막을 만들 수 있었다. 분석 장비로는 박막의 결정화도를 측정하기 위해 GAXRD (glancing angle X-ray diffractometer)를 사용하였고, 잔여 하는 금속의 양과 화학적 결합 상태를 알아보기 위해 XPS를 통해 분석을 하였다. 마지막으로 홀 속도와 비저항을 측정하기 위해 Hall measurement와 Four-point prove를 사용하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Korean Journal of Materials Research
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• v.14 no.7
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• pp.477-481
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• 2004

High quality polycrystalline silicon is very critical part of the high quality thin film transistor(TFT) for display devices. Metal induced lateral crystallization(MILC) is one of the most successful technologies to crystallize the amorphous silicon at low temperature(below $550^{\circ}C$) and uses conventional and large glass substrate. In this study, we observed that the MILC behavior changed with abrupt variation of the amorphous silicon active pattern width. We explained these phenomena with the novel MILC mechanism model. The 10 nm thick Ni layers were deposited on the glass substrate having various amorphous silicon patterns. Then, we annealed the sample at $550^{\circ}C$ with rapid thermal annealing(RTA) apparatus and measured the crystallized length by optical microscope. When MILC progress from narrow-width-area(the width was $w_2$) to wide-width-area(the width was $w_1$), the MILC rate decreased dramatically and was not changed for several hours(incubation time). Also the incubation time increased as the ratio, $w_1/w_2$, get larger. We can explain these phenomena with the tensile stress that was caused by volume shrinkage due to the phase transformation from amorphous silicon to crystalline silicon.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.2
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• pp.93-97
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• 2003

The crystallization behavior of amorphous silicon is affected by direction and intensity of electric field in FALC（Field-Aided Lateral Crystallization). Electric field was calculated in a simplified model using conductivity data of Mo, a-Si, $SiO_2$and boundary conditions for electric potential at the electrodes. The magnitude of electric field intensity in each corner of cathode was much larger than that in the center of patterns, and the electric field direction was 50~60 degree outside to cathode. And electric field intensity at a relatively small pattern was larger than that of a large pattern.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1203-1207
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• 2008

For a large sized, ultra definition (UD) and high refresh rate for motion blur free AMLCD TVs, amorphous IGZO thin film transistor (TFT) are applied and investigated in terms of threshold voltage ($V_{th}$) shift influenced by active layer thickness uniformity, source drain etching technology, heat treatment and passivation condition. Optimizing above parameters, we fabricated the world's largest 15 inch XGA AMLCD successfully.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.553-556
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• 2008

We hereby report novel driving scheme to eliminate effect of "residual" image sticking (RRI) problem which arises due to hysteresis problem in Thin Film Transistor (TFT) in AMOLED Displays. The driving scheme applies "black" voltage after every data voltage period in order to drive AMOLED in uni-direction. The system can be easily implemented with 120 Hz driving scheme which is well matured in AMLCD industries. Our analyses show systematic evaluation of the problem and thereby solving it by simple methods which will be significantly effective of driving OLED towards mass manufacturing stage.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.295-298
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• 2003

Reflective mode liquid crystal on silicon (LCoS) microdisplay is the major technology that can produce extremely high-resolution displays. A very large number of pixels can be packed onto the CMOS circuit with integrated drivers that can be projected to any size screen. Large size direct-view thin film transistor (TFT) LCDs becomes very difficult to make and to drive as the information content increases. However, the existing LC alignment technology for the LCoS cell fabrication is still the mechanical rubbing method, which is prone to have minor defects that are not visible normally but can be detrimental if projected to a large screen. In this paper, application of photo-alignment to LCoS fabrication is presented. The alignment is done by three-step exposure process. A MTN $90^{\circ}$ mode is chose as to evaluate the performance of this technique. The comparison with rubbing mode shows the performance of photo-alignment is comparable and even better in some aspect, such as sharper RVC curve and higher contrast ratio.