• Design & Manufacturing
• /
• v.2 no.2
• /
• pp.29-32
• /
• 2008

A back light unit (BLU) is a key module of a thin film transistor liquid crystal display (TFT-LCD), frequently utilized in various mobile displays. In this study, we experimentally characterize transcription and optical properties of concave and convex microlens arrays (MLAs) of light guide plate (LGP) fabricated by injection molding with polycarbonate as a LGP substrate material. Nickel mold inserts were manufactured by electroforming on the MLA which was fabricated by the thermal reflow of photoresist microstructures patterned by UV-photolithography. For the case of convex microlens, the height of replicated microlens was less than that of the mold insert while maintaining almost the same microlens diameter of the mold insert as the location of the microlens is far from the gate. In contrast, for the concave microlens, the diameter of replicated microlens was larger than that of mold insert, while showing almost the same microlens height as the mold insert. From the optical examination of replicated convex and concave MLAs, it was found that a higher luminance of the LGP was achieved by the concave MLAs compared to the convex MLAs (about 30% enhancement in this case)due to the utilization of a larger amount of light provided by the light sources.

• Journal of the Korean Society for Heat Treatment
• /
• v.27 no.5
• /
• pp.230-234
• /
• 2014

IGZO/Ag bi-layered films were deposited on glass substrate at room temperature with radio frequency and direct current magnetron sputtering, respectively to consider the effect of Ag buffer layer on the electrical, optical and structural properties. For all deposition, while the thickness of Ag buffer layer was varied as 10, 15, and 20 nm, The thickness of IGZO films were kept at 100 nm, In a comparison of figure of merit, IGZO films with 15 nm thick Ag buffer layer show the higher figure of merit ($1.1{\times}10^{-2}{\Omega}^{-1}$) than that of the IGZO single layer films ($3.7{\times}10^{-4}{\Omega}^{-1}$). From the observed results, it is supposed that the IGZO 100 nm/Ag 15 nm bi-layered films may be an alternative candidate for transparent electrode in a transparent thin film transistor device.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07a
• /
• pp.61-63
• /
• 2005

Pentacene based OTFT on PC and PES plastic substrates have been fabricated in a scale of 5 inches. We could get a small OTFT device enough to be applicable for AMOLED by acquiring the at least misalignment margin through a contact aligner. And also we could find out the degradation of device parameter through the integration processes and improve the properties by using a buffer layer as an etch stopper in an active patterning. Through these, the mobility of device is more than about $0.2cm^2/Vs$ and $I_{on}/I_{off}$ is higher than $10^5$.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.9
• /
• pp.623-627
• /
• 1999

We report a new in-situ fluorine passivation method without in implantation by employing excimer laser annealing of $SiO_{x}F_{y}$/a-Si structure and its effects on p-channel poly-Si TFTs. The proposed method doesn't require any additional annealing step and is a low temperature process because fluorine passivation is simultaneous with excimer-laser-induced crystallization. A in-situ fluorine passivation by the proposed method was verified form XPS analysis and conductivity measurement. From experimental results, it has been shown that the proposed method is effective to improve the electrical characteristics, specially field-effect mobility, and the electrical stability of p-channel poly-Si TFTs. The improvement id due to fluorine passivation, which reduces the trap state density and forms the strong Si-F bonds in poly-Si channel and $SiO_2/poly-Si$ interface. From these results, the high performance poly-Si TFTs canbe obtained by employing the excimer-laser-induced fluorine passivation method.

• Journal of the Korean Applied Science and Technology
• /
• v.24 no.1
• /
• pp.54-60
• /
• 2007

이 논문에서는 게이트 절연막 위에 vapor deposition polymerization(VDP)방법을 사용하여 성막한 유기 점착층을 진공 열증착하여 유기 박막 트랜지스터(OTFTs)소자를 제작할 수 있음을 증명하였다. 우리가 제작한 Staggered-inverted top-contact 구조를 사용한 유기 박막 트랜지스터는 전기적 output 특성이 포화 영역안에서는 포화곡선을, triode 영역에서는 비선형적인 subthreshold를 확실히 볼 수 있음을 발견했다. $0.2{\mu}m$ 두께를 가진 게이트 절연막위에 유기 점착층을 사용한 OTFTs의 장 효과 정공의 이동도와 문턱전압, 그리고 절멸비는 각각, 약 0.4cm2/Vs, -0.8V, 106 이 측정되었다. 게이트 절연막의 점착층으로써 폴리이미드의 성막을 위해, 스핀코팅 방법 대신 VDP 방법을 도입하였다. 폴리이미드 고분자막은 2,2bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride(6FDA)와 4,4'-oxydianiline(ODA)을 고진공에서 동시에 열 증착 시킨 후, 그리고 $150^{\circ}C$에서 1시간, 다시 $200^{\circ}C$에서 1시간 열처리하여 고분자화된 막을 형성하였다. 그리고 점착층이 OTFTs의 전기적 특성에 주는 영향을 설명하기 위해 비교 연구하였다.

• Journal of Adhesion and Interface
• /
• v.20 no.4
• /
• pp.155-161
• /
• 2019

Understanding charge transport anisotropy at the interface of conjugated nanostructures basically gives insight into structure-property relationship in organic field-effect transistors (OFET). Here, the anisotropy of the field-effect mobility at the interface between 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) single crystal with cofacial molecular stacks in a-b basal plane and SiO gate dielectric was investigated. A solvent exchange method has been used in order for TIPS-pentacene single crystals to be grown on the surface of SiO₂ thin film, corresponding to the charge accumulation at the interface in OFET structure. In TIPS-pentacene OFET, the anisotropy ratio between the highest and lowest measured mobility is revealed to be 5.2. By analyzing the interaction of a conjugated unit in TIPS-pentacene with the nearest neighbor units, the mobility anisotropy can be rationalized by differences in HOMO-level coupling and hopping routes of charge carriers. The theoretical estimation of anisotropy based on HOMO-level coupling is also consistent with the experimental result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.168-168
• /
• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Proceedings of the KIEE Conference
• /
• 2006.10a
• /
• pp.50-52
• /
• 2006

본 논문은 고성능 다결정 실리콘(Poly-Si) 박막 트랜지스터 (Thin Film Transistor)에서 단일 수직 그레인 경계(Single Perpendlcular Grain Boundary)가 고온 캐리어 스트레스(Hot Carrier Stress) 및 정전류 안정성 평가에서 어떠한 효과를 보이는가에 대해서 살펴보았다. 고온 캐리어 스트레스 하에서($V_G=V_{TH}+1V,\;V_D$ =12V),그레이 경계가 없는 다결정 실리콘 TFT와 비교했을 때 그레인 경계를 가지고 있는 다결정 실리를 TFT는 전기 전도(Electric Conduction)에 작용하는 자유 캐리어(Free Carrier)의 개수가 적기 때문에 상대적으로 더욱 우수한 전기적 특성을 나타낸다. 먼저 1000초 동안 고온 캐리어 스트레스를 가해준 결과 단일 그레인 경계를 가진 다결정 실리콘에서의 트랜스 컨덕턴스(Transconductance)의 이동 정도는 5% 미만으로 확인되었다. 반면에 같은 스트레스 조건 하에서 그레인 경계가 존재하지 않는 다결정 실리콘의 경우에는 그 이동 정도가 약 25%에 달하는 것으로 측정되었다. 다음으로 정전류 스트레스(Constant Current Stress) 인가시, 수직형 그레인 경계가 채널 영역 내에 존재하지 않는 다결정 실리콘 TFT는 드레인 접합 부분의 전계 세기를 비교했을 때, 그레인 경계를 가지고 있는 다결정 실리콘 TFT보다 상대적으로 낮은 원 인 때문에 적게 열화되는(Degraded) 특성을 확인할 수 있었다.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2009.05a
• /
• pp.13.1-13.1
• /
• 2009

Transparent electronics has attracted many interests, for it can open new applications for consumer electronics, transportation, business, and military. Among them, display backplane, thin film transistor (TFT) array would be the most attractive application. Many researchers have been investigating oxide semiconductors for transparent channel material of TFT since the report for transparent amorphous oxide semiconductor (TAOS) TFT by Hosono group and ZnO TFT by Wager group. Especially, oxide TFTs have been intensively investigated during a couple of years since the first demonstration of ZnO-TFT driving AM-OLED. Many papers regarding the fabrication and performance of oxide TFTs, and active matrix display driven by oxide TFTs have been reported. Now lots of people have confidence in the competitiveness of oxide TFTs for the backplane of AM-Display. Especially, high mobility, uniformity, fairly good stability, and low cost process make oxide TFTs applied even to a large size AM-OLED. Last year, Samsung mobile display, former SID, reported 12" AM-OLED driven by IZGO-TFT and it seems that the remained issue for the mass production is the bias temperature stability. Here, we will introduce the application of oxide TFT and important issue for oxide TFT to be used for the direct printing.

• Electrical & Electronic Materials
• /
• v.9 no.1
• /
• pp.30-37
• /
• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.