• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.737-739
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• 1998

Gate insulators using various fluoride films were investigated for thin film transistor applications. Conventional oxide containing materials exhibited high interface states, high $D_{it}$ gives an increased threshold voltage and poor stability of TFT. To improve TFT performances, we must reduce interface trap charge density between Si and gate insulator. In this paper, we investigated gate insulators such as such as $CaF_2$, $SrF_2$, $MgF_2$ and $BaF_2$. These materials exhibited an improvement in lattice mismatch, difference in thermal expansion coefficient, and electrical stability MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 0.737%, breakdown electric field higher than 1.7MV/cm and leakage current density of $10^{-6}A/cm^2$. This paper probes a possibility of new gate insulator material for TFT application.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.352-357
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• 1999

The Cu sheets were selected for the substrate of the superconductor films. Pure Cu sheets with the thickness of 50${\mu}$m were fabricated using hot and cold rolling. The Cu sheets were heat treated to induce the biaxial texturing. The z-axis and x-y plane texturing of Cu sheets heat treated at different conditions were analyzed using XRD and a best heat treatment condition for the texturing was selected. ZrO$_2$ film was dip coated on Cu sheets heat treated at the best condition to prevent possible reaction between Cu sheets and YBCO superconductors, to reduce possible cracking due to thermal expansion mismatch and to decrease the lattice mismatch for biaxial texturing. The texturing of the oxide buffer layers were also studied.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.240-240
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• 2010

반사 방지막은 LEDs, 태양전지, 센서 등의 광전소자의 효율을 향상시키는데 사용되고 있다. 일반적으로 사용되는 단층 또는 다층 박막의 반사방지막은 thermal expansion mismatch, adhesion, stability 등의 문제점을 가지고 있다. 따라서, 단층 또는 다층 박막의 반사방지막 대신에 파장이하의 주기를 갖는 구조(subwavelength structure, SWS)의 반사방지막 연구가 활발히 진행되고 있다. 입사되는 태양 스펙트럼의 파장보다 작은 주기를 갖는 SWS 구조는 Fresnel 반사율을 감소시켜 빛의 손실을 줄일 수 있다. 이러한 SWS 반사 방지막을 제작하기 위해서는 에칭 마스크가 필요하다. 에칭 마스크 제작을 위해서 사용되는 장비로는 홀로그램, 전자빔, 나노임프린트와 같은 리소그라피 방법이 있으나, 이들은 제작 비용이 고가이며 복잡한 기술을 필요로 한다. 따라서 본 실험에서는 리소그라피 방법보다 간단하고 저렴한 self-assembled Au 나노 입자 에칭 마스크를 이용한 실리콘 SWS 반사 방지막을 제작하여 구조적 및 광학적 특성을 연구하였다. Au박막은 열증발증착(thermal evaporator)법에 의해 실리콘 기판 위에 증착되었고, 급속 열처리(rapid thermal annealing, RTA)를 통해 Au 나노입자 에칭 마스크를 형성시켰다. 실리콘 SWS 반사방지막은 식각 가스 $SiCl_4$를 기반의 유도결합 플라즈마(inductively coupled plasma, ICP) 장비를 사용하여 제작되었다. Au 나노 입자의 마스크 패턴 및 에칭된 실리콘 SWS 프로파일은 scanning electron microscope를 사용하여 관찰하였으며, UV-Vis-NIR spectrophotometer를 사용하여 300-1100 nm 파장 영역에 따른 반사율을 측정하였다. ICP 에칭 조건을 변화시켜 가장 낮은 반사율을 갖는 최적화된 실리콘 SWS 반사방지막을 도출하였다. 최적화된 구조에 대해서, 실리콘 SWS 반사방지막은 벌크 실리콘 (>35%)보다 더 낮은 5% 이하의 반사율을 나타냈다.

• Steel and Composite Structures
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• v.19 no.6
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• pp.1501-1510
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• 2015

The frequency selective surface (FSS) embedded hybrid composite materials have been developed to provide excellent mechanical and specific electromagnetic properties. Radar absorbing structures (RASs) are an example material that provides both radar absorbing properties and structural characteristics. The absorbing efficiency of an RAS can be improved using selected materials having special absorptive properties and structural characteristics and can be in the form of multi-layers or have a certain stacking sequence. However, residual stresses occur in FSS embedded composite structures after co-curing due to a mismatch between the coefficients of thermal expansion of the FSS and the composite material. In this study, to develop an RAS, the thermal residual stresses of FSS embedded composite structures were analyzed using finite element analysis, considering the effect of stacking sequence of composite laminates with square loop (SL) and double square loop (DSL) FSS patterns. The FSS radar absorbing efficiency was measured in the K-band frequency range of 21.6 GHz. Residual stress leads to a change in the deformation of the FSS pattern. Using these results, the effect of transmission characteristics with respect to the deformation on FSS pattern was analyzed using an FSS Simulator.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Transactions of the Korean Society of Automotive Engineers
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• v.4 no.6
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• pp.18-26
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• 1996

A two dimensional thermo elasto-plastic finite element stress analysis was performed to study residual stress distributions in AI composites reinforced by SiC whisker and $ZrO_2$ ceramic joints. The influences on the residual stress distributions due to the difference of the reinforcement volume fraction and interlayer material property were investigated. Specifically, stress distributions between AI interlayer material property were investigated. Specifically, stress distributions between AI interlayer and $ZrO_2$ ceramic and between the AI interlayer and AI composite were computationally analzed.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.470-475
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• 1999

ZnS and ZnTe epilayers were grown on GaAs(100) GaP(100) substrates by hot-wall eitaxy. X-ray diffraction revealed that the epilayers have zinc-blende structure and were grown in (100) direction. The small values of the full width at half maximum (FWHM) of double crystal rocking curve (DCRC) showed high quality of the epilayers. From the thickness dependence of the FWHM of DCRC, the strain remaining in films is found to be due to the thermal expansion difference as well as due to the lattice mismatch.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2003.10a
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• pp.167-170
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• 2003

In this paper, the electromechanical displacements of curved actuators using laminated composites are calculated by finite element method to design the optimal configuration of curved actuators. To predict the pre-stress in the device due to the mismatch in coefficients of thermal expansion, the carbon-epoxy and glass- epoxy as well as PZT ceramic is also numerically modeled by using hexahedral solid elements. Because the modeling of these thin layers causes the numbers of degree of freedom to increase, large-scale structural analyses are performed in a cluster system in this study. The curved shape and pre-stress in the actuator are obtained by the cured curvature analysis. The displacement under the piezoelectric force by an applied voltage is also calculated to compare the performance of curved actuator. The thickness of composite is chosen as design factor.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2003.10a
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• pp.207-210
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• 2003

Vacuum hot pressing has been used for the development of Ti-MMCs using foil-fiber-foil method, and subsequent micro-mechanical characteristics of the composites are evaluated by means of several experimental processes. As shown by the results, fiber strength degradation occurs during the consolidation, and particularly residual stresses results from the thermal expansion mismatch between fiber and matrix materials during cooling process are incorporated in the changes of mechanical properties of the composites. In industrial applications, the processing conditions avoiding micro-material failures are important together with the properties of finished products, and therefore should be included in the assesment of the material characterization.