• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.106-107
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• 2007

We fabricated anodic aluminium oxides (AAO) on Si and sapphire substrates from the electrochemical reactions of thin AI films in an aqueous solution of oxalic acid. The thin AI films have deposited on Si and Sapphire substructure by using E-beam evaporation and thermal evaporation, respectively. The formation of AAO structures has investigated from FE-SEM measurement image and showed randomly distributed phase of nanoholes instead of the periodic lattice of photonic crystals. The AAO structure on sapphire shows the double layers of nanoholes.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.39.2-39.2
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• 2011

With the steady increase in the demand for flexible devices, mainly in display panels, researchers have focused on finding a novel material that have excellent electrical properties even when it is bended or stretched, along with superior mechanical and thermal properties. Graphene, a single-layered two-dimensional carbon lattice, has recently attracted tremendous research interest in this respect. However, the limitations in the growing method of graphene, mainly chemical vapor deposition on transition metal catalysts, has posed severe problems in terms of device integration, due to the laborious transfer process that may damage and contaminate the graphene layer. In addition, to lower the overall cost, a fabrication technique that supports low temperature and low vacuum is required, which is the main reason why solution-based process for graphene layer deposition has become the hot issue. Nonetheless, a direct deposition method of large area, few-layered, and uniform graphene layers has not been reported yet, along with a convenient method of patterning them. Here, we report an evaporation-induced technique for directly depositing few layers of graphene nanosheets with excellent uniformity and thickness controllability on any substrate. The printed graphene nanosheets can be patterned into desired shapes and structures, which can be directly applicable as flexible and transparent electrode. To illustrate such potential, the transport properties and resistivity of the deposited graphene layers have been investigated according to their thickness. The induced internal flow of the graphene solution during tis evaporation allows uniform deposition with which its thickness, and thus resistivity can be tuned by controlling the composition ratio of the solute and solvent.

• Journal of Biosystems Engineering
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• v.34 no.1
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• pp.44-49
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• 2009

This study was conducted to investigate the pyrolysis characteristics of switchgrass using TGA-FTIR instrument. Switchgrass is a high yielding perennial grass that has been designated as a potential energy crop, because of its high energy value. Ground switchgrass were pyrolysed at different heating rates of 10, 20, 30, and $40^{\circ}C/min$ in a TGA-FTIR instrument. The thermal decomposition characteristics of switchgrass were analyzed, and the gases volatilized during the experiment were identified. The thermal decomposition of switchgrass started at approximately $220^{\circ}C$, followed by a major loss of weight, where the main volatilization occurred, and the thermal decomposition was essentially completed by $430^{\circ}C$. The pyrolysis process was found to compose of four stages; moisture evaporation, hemicellulose decomposition, cellulose decomposition, and lignin degradation. The peak temperatures for hemicellulose decomposition ($306^{\circ}C$ to $327^{\circ}C$) and cellulose decomposition ($351^{\circ}C$ to $369^{\circ}C$) were increased with greater heating rates. FTIR analysis showed that the following gases were released during the pyrolysis of switchgrass; $CO_2$, CO, $CH_4$, $NH_3$, COS, $C_{2}H_{4}$, and some acetic acid. The most gas species were released at low temperature from 310 to $380^{\circ}C$, which was corresponding well with the observation of thermal decomposition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.243-243
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• 2009

Bi2O3 doped ZnO nanostructures structure were successfully synthesized by a thermal evaporatiion process and their structural characteristics were investigated. It is demonstrated that the growth condition such as the areal density, pretreatment of the substrates and growth temperature have great influence on the morphology and the alignment of the nanorods arrays. The density of Bi2O3 doped ZnO nanostructures is controlled by the gold (Au) nanoparticle density deposited on the silicon substrates. Relatively homogenous size and shape were observed by introducing gold(Au) seed-layer as nucleation centers on the substrates prior to the VLS reaction. The samples were characterized by X-ray diffraction, scanning electron microscopy.

• Korean Journal of Materials Research
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• v.15 no.7
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• pp.435-438
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• 2005

Single phase $Zn_4Sb_3$ with $98.5\%$ of theoretical density was successfully produced by direct hot pressing of elemental powders containing $1.2 at\%$ excess Zn for compensating the evaporation during the process. Temperature dependences of thermoelectric properties were investigated from 4 K to 300 K. Seebeck coefficient, electrical conductivity, thermal conductivity as well as thermoelectric figure of merit showed the discontinuity in variation at 242K, indicating the $\alpha-\beta$, phase transformation. Interestingly, it was found that lattice thermal conductivity by phonons is dominant in total thermal conductivity of $\alpha-\beta$. Therefore, it is expected that thermoelectric properties can be improved by reduction of lattice thermal conductivity inducing lattice scattering centers by doping and solid solution.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.562-562
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• 2012

Recently, graphene and graphene-based materials such as graphene oxide (GO) or reduced graphene oxide (R-GO) draws a great attention for electronic devices due to their structures of one atomic layer of carbon hexagon that have excellent mechanical, electrical, thermal, optical properties and very high specific surface area that can be high potential for chemical functionalization. R-GO is a promising candidate because it can be prepared with low-cost from solution process by chemical oxidation and exfoliation using strong acids and oxidants to produce graphene oxide (GO) and its subsequent reduction. R-GO has been used as semiconductor or conductor materials as well as sensing layer for bio-molecules or ions. In this work, reduced graphene oxide field-effect transistor (R-GO FET) has been fabricated with ITO extended gate structure that has sensing area on ITO extended gate part. R-GO FET device was encapsulated by tetratetracontane (TTC) layer using thermal evaporation. A thermal annealing process was carried out at $140^{\circ}C$ for 4 hours in the same thermal vacuum chamber to remove defects in R-GO film before deposition of TTC at $50^{\circ}C$ with thickness of 200 nm. As a result of this process, R-GO FET device has a very high stability and durability for months to serve as a transducer for sensing applications.

• Journal of the Korean institute of surface engineering
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• v.50 no.6
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• pp.465-472
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• 2017

The ingot fabrication conditions related with the thermal shock bearing phase and microstructure have investigated for the rare earth zirconate ceramic material, lanthanum gadolinium zirconate, as a thermal barrier coating using electron beam evaporation method. The thermal shock resistance of the prepared ingot was evaluated by high energy electron beam irradiation. The rare earth zirconate ceramic powder was prepared by controlling the raw material powder composition of $La_2O_3$, $Gd_2O_3$ and $ZrO_2$ so as to have a composition of $(La_{0.3}Gd_{0.7})_2Zr_2O_7$ which was selected from the former study. Ingot samples were prepared under two conditions. The first condition is prepared by sintering the prepared powder mixture to form an ingot. The second condition is prepared by calcining the prepared powder mixture to form a composite phase and then sintering to form an ingot. X-ray diffraction(XRD) and Scanning Electron Microscope(SEM) were used to analyze phase forming behavior and microstructure of ingot samples. Nanoindentation method used to obtain elastic modulus and hardness of each ingot specimen. Also the stress distribution of ingot was simulated by using FEM method assuming the ingot surface was exposed to electron beam. As a results, in the case of an ingot having a network-shaped microstructure in which relatively coarse pores are included, it seems that the thermal shock resistance was higher than in the case of an ingot having a microstructure composed of relatively fine grains only or particles with the similar level size when the high energy electron beam irradiation.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.27-32
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• 2020

This study proposes a pixel-patterning method for organic light-emitting diodes (OLEDs) based on thermal transfer. An infrared lamp was introduced as a heat source, and glass type donor element, which absorbs infrared and generates heat and then transfers the organic layer to the substrate, was designed to selectively sublimate the organic material. A 200 nm-thick layer of molybdenum (Mo) was used as the lightto-heat conversion (LTHC) layer, and a 300 nm-thick layer of patterned silicon dioxide (SiO₂), featuring a low heat-transfer coefficient, was formed on top of the LTHC layer to selectively block heat transfer. To prevent the thermal oxidation and diffusion of the LTHC material, a 100 nm-thick layer of silicon nitride (SiN_x) was coated on the material. The fabricated donor glass exhibited appropriate temperature-increment property until 249 ℃, which is enough to evaporate the organic materials. The alpha-step thickness profiler and X-ray reflection (XRR) analysis revealed that the thickness of the transferred film decreased with increase in film density. In the patterning test, we achieved a 100 ㎛-long line and dot pattern with a high transfer accuracy and a mean deviation of ± 4.49 ㎛. By using the thermal-transfer process, we also fabricated a red phosphorescent device to confirm that the emissive layer was transferred well without the separation of the host and the dopant owing to a difference in their evaporation temperatures. Consequently, its efficiency suffered a minor decline owing to the oxidation of the material caused by the poor vacuum pressure of the process chamber; however, it exhibited an identical color property.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.