• 제목/요약/키워드: The Simulated Annealing

검색결과 626건 처리시간 0.026초

Efficient Rate Control by Fast Adaptive Mode Selection

  • Ryu, Chul
    • The Journal of the Acoustical Society of Korea
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    • 제18권4E호
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    • pp.43-50
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    • 1999
  • A fast converging coding algorithm that adaptively selects the modes of macroblocks is introduced. For a given frame, the optimal modes are selected based on the decision curves that minimize the overall distortion at a given bit rate. The method proposed in this paper is different from the conventional ones in that it does not manipulate the quantizer to meet the target bit rate but it satisfies the target bit rate by finding optimal modes of macroblocks which result consistent visual quality. Lagrange multiplier of the unconstrained cost function is controlled to trigger decision curves to generate appropriate modes to meet bit rate and the curve is obtained by utilizing simulated annealing optimization technique. The algorithm is implemented within H.261 video codec and simulation results demonstrate superior visual quality.

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Field programmable circuit board를 위한 위상 기반 회로 분할 (A topology-based circuit partitioning for field programmable circuit board)

  • 최연경;임종석
    • 전자공학회논문지C
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    • 제34C권2호
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    • pp.38-49
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    • 1997
  • In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

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그래프 이론을 이용한 설비배치 계획에 관한 연구 (A Study on Facility Layout Planning Using Graph Theory)

  • 김재곤;이근철;김영대
    • 대한산업공학회지
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    • 제23권2호
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    • pp.359-370
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    • 1997
  • We consider a facility layout problem with the objective of minimizing total transportation distance, which is the sum of rectilinear distances between facilities weighted by the frequency of trips between the facilities. It is assumed that facilities are required to have rectangular shapes and there is no empty space between the facilities in the layout. In this study, a graph theoretic heuristic is developed for the problem. In the heuristic, planar graphs are constructed to represent adjacencies between the facilities and then the graphs are converted to block layouts on a continual plane using a layout construction module. (Therefore, each graph corresponds to a layout.) An initial layout is obtained by constructing a maximal weighted planar graph and then the layout is improved by changing the planar graph. A simulated annealing algorithm is used to find a planar graph which gives the best layout. To show the performance of the proposed heuristic, computational experiments are done on randomly generated test problems and results are reported.

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타부탐색(Tabu Search)의 확장모델을 이용한 '외판원 문제(Traveling Salesman Problem)' 풀기

  • 고일상
    • 한국경영과학회:학술대회논문집
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    • 한국경영과학회 1996년도 추계학술대회발표논문집; 고려대학교, 서울; 26 Oct. 1996
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    • pp.135-138
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    • 1996
  • In solving the Travel Salesman Problem(TSP), we easily reach local optimal solutions with the existing methods such as TWO-OPT, THREE-OPT, and Lin-Kernighen. Tabu search, as a meta heuristic, is a good mechanism to get an optimal or a near optimal solution escaping from the local optimal. By utilizing AI concepts, tabu search continues to search for improved solutions. In this study, we focus on developing a new neighborhood structure that maintains the feasibility of the tours created by exchange operations in TSP. Intelligent methods are discussed, which keeps feasible tour routes even after exchanging several edges continuously. An extended tabu search model, performing cycle detection and diversification with memory structure, is applied to TSP. The model uses effectively the information gathered during the search process. Finally, the results of tabu search and simulated annealing are compared based on the TSP problems in the prior literatures.

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메탈-메탈 매트릭스 레이아웃 형태의 기능모듈 생성 (Functional Module Generation in Metal-Metal Matrix($M^3$) Layout Style)

  • 차영준;임종석
    • 전자공학회논문지A
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    • 제32A권1호
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    • pp.206-221
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    • 1995
  • Metal-Metal Matrix(M$^{3}$) layout is a recently proposed layout style which uses minimum amount of poly wires for high speed operation. In this paper we propose a method of generating functional modules in M$^{3}$ layout style. In the proposed method the transistors and the input/output lines of the given circuit are first placed in M$^{3}$ layout style and then they are interconnected using two metal layers. We develop a new placement method by simulated annealing, and we modify the well known channel routing method for the interconnections. When we applied our method to several logic circuits, the area of the generated layout is smaller than the ones by the previously known method. Our results also compares favorably to the other layout styles like gate matrix layout.

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CSP와 SA를 이용한 Job Shop 일정계획에 관한 연구 (A Study on the Job Shop Scheduling Using CSP and SA)

  • 윤종준;손정수;이화기
    • 산업경영시스템학회지
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    • 제23권61호
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    • pp.105-114
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    • 2000
  • Job Shop Problem which consists of the m different machines and n jobs is a NP-hard problem of the combinatorial optimization. Each job consists of a chain of operations, each of which needs to be processed during an uninterrupted time period of a given length on a given machine. Each machine can process at most one operation at a time. The purpose of this paper is to develop the heuristic method to solve large scale scheduling problem using Constraint Satisfaction Problem method and Simulated Annealing. The proposed heuristic method consists of the search algorithm and optimization algorithm. The search algorithm is to find the solution in the solution space using CSP concept such as backtracking and domain reduction. The optimization algorithm is to search the optimal solution using SA. This method is applied to MT06, MT10 and MT20 Job Shop Problem, and compared with other heuristic method.

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공장 자동화를 위한 다열 배치에서의 작업자 할당 (Workforce Assignment in Multiple Rowsfor Factory Automation)

  • 김채복
    • 산업경영시스템학회지
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    • 제27권2호
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    • pp.68-77
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    • 2004
  • This paper considers the workforce assignment problem to minimize both the deviations of workloads assigned to workers and to maximize the total preference between each worker and each machine. Because of the high expense of technology education and the difficulties of firing employees, there is no part time workers in semiconductor industry. Therefore, multi-skilled workers are trained for performing various operations in several machines. The bicriteria workforce assignment problem in this paper is not easy to obtain the optimal solution considering the aisle structure and it is belong to NP-class. The proposed heuristic algorithms are developed based on the combination of spacefilling curve technique, simulated annealing technique and graph theory focusing on the multiple-row machine layout. Examples are presented for the proposed algorithms how to find a good solution.

A Modified FCM for Nonlinear Blind Channel Equalization using RBF Networks

  • Han, Soo-Whan
    • Journal of information and communication convergence engineering
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    • 제5권1호
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    • pp.35-41
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    • 2007
  • In this paper, a modified Fuzzy C-Means (MFCM) algorithm is presented for nonlinear blind channel equalization. The proposed MFCM searches the optimal channel output states of a nonlinear channel, based on the Bayesian likelihood fitness function instead of a conventional Euclidean distance measure. In its searching procedure, all of the possible desired channel states are constructed with the elements of estimated channel output states. The desired state with the maximum Bayesian fitness is selected and placed at the center of a Radial Basis Function (RBF) equalizer to reconstruct transmitted symbols. In the simulations, binary signals are generated at random with Gaussian noise. The performance of the proposed method is compared with that of a hybrid genetic algorithm (GA merged with simulated annealing (SA): GASA), and the relatively high accuracy and fast searching speed are achieved.

OPTIMAL PERIOD SELECTION TO MINIMIZE THE END-TO-END RESPONSE TIME

  • SHIN M.;LEE W.;SUNWOO M.
    • International Journal of Automotive Technology
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    • 제6권1호
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    • pp.71-77
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    • 2005
  • This paper presents a systematic approach which determines the optimal period to minimize performance measure subject to the schedulability constraints of a real-time control system by formulating the scheduling problem as an optimal problem. The performance measure is derived from the summation of end-to-end response times of processed I/Os scheduled by the static cyclic method. The schedulability constraint is specified in terms of allowable resource utilization. At first, a uniprocessor case is considered and then it is extended to a distributed system connected through a communication link, local-inter network, UN. This approach is applied to the design of an automotive body control system in order to validate the feasibility through a real example. By using the approach, a set of optimal periods can easily be obtained without complex and advanced methods such as branch and bound (B&B) or simulated annealing.

명령어 해독기 설계를 위한 출력 부호화 방법 (Output encoding methods for the design of insturction decoder)

  • 김한흥;황승호;경종민
    • 전자공학회논문지A
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    • 제31A권10호
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    • pp.132-140
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    • 1994
  • In this paper, we consider the area-minimal implementation of the instruction decoder for microprogrammed processors such as modern CISC-type microprocessor. We formulate it as a constrained output encoding problem and, based on simulated annealing algorithm, propose efficient heuristic solution methods both for PLA and multi-level implementation of the decoder. Experimental results on various examples show that our methods produce, on the average, 10~40% reduction of the number of product terms for the PLA implementations and 9.8~34.4% reduction of the number of literal for the multi-level implementations compared to the results of random encoding method.

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