• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.43 no.3
• /
• pp.504-514
• /
• 1994

Combinational automatic test pattern generators (CATPG) have already been commercialized because their algorithms are well known and practical, while sequential automatic test pattern generators(SATPG) have been regarded as impractical because they are computationally complex. A technique to use CATPG instead of SATPG for test generation of sequential circuits is proposed. Redesign of seauential circuits such as Level Sensitive Scan Design (LSSD) is inevitable to use CATPG. Various partial scan techniques has been proposed to avoid full scan such as LSSD. It ha sbeen reported that SATPG is required to use partial scan techniques. We propose a technique to use CATPG for a new partial scan technique, and propose a new CATPG algorithm for the partially scanned circuits. The partial scan technique can be another choice of design for testability because it is computationally advantageous.

• Journal of KIISE:Software and Applications
• /
• v.33 no.1
• /
• pp.44-57
• /
• 2006

With the rapid growth of network technology, two or more products from different vendors are integrated and interact with each other to perform a certain function in the latest systems. Thus. interoperability testing is considered as an essential aspect of correctness of integrated systems. Interoperability testing is to test the ability of software and hardware on different machines from different vendors to share data. Most of the researches model communication system behavior using EFSM(Extended Finite State Machines) and use EFSM as an input of test scenario generation algorithm. Actually, there are many studies on systematic and optimal test case generation algorithms using EFSM. But in these researches, the study for generating EFSM model which is a foundation of test scenario generation isn't sufficient. This study proposes an EFSM generating technique from informal requirement analysis document for more complete interoperability testing. and implements prototype of Test Case Generation Tool generating test cases semi-automatically. Also we describe theoretical base and algorithms applied to prototype implementation.

• KIPS Transactions on Software and Data Engineering
• /
• v.6 no.8
• /
• pp.401-410
• /
• 2017

This paper proposes a method to generate test cases in an automatic manner, based on checklist containing test cases used for testing embedded systems. In general, the items to be tested are defined in a checklist. However, most test case generation strategies recommend to test a system with not only the defined test items but also various mutated test conditions. The proposed method parses checklist in Korean file and figures out the system inputs and outputs, and operation information. With the found information and the user defined test case generation strategy, the test cases are automatically generated. With the proposed method, the errors introduced during manual test case generation may be reduced and various test cases not defined in checklist can be generated. The proposed method is implemented and the experiment is performed with the checklist for an medical embedded system. The feasibility of the proposed method is shown through the test cases generated from the checklist. The test cases are adequate to the coverages and their statistics are correct.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.5
• /
• pp.661-670
• /
• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

• Journal of KIISE:Software and Applications
• /
• v.36 no.5
• /
• pp.361-375
• /
• 2009

The major concern of component users who develop applications using the existing components is to confirm whether a component is collaborating with the different components in accordance with the requirements. Therefore, interoperability testing whose role is to check whether components collaborate with each other within the new operating environment not within the component development content of each component is considered as an importance research topic. In this paper, we propose a test case generation technique for interoperability test of component based software. The proposed technique defines a test model for generating test cases. The proposed technique generates test models from the use case specification and thereafter from these models, test cases for Interoperability testing are derived. In addition, we describe a tool which Implements the procedures for generating test sequences from test models.

• The KIPS Transactions:PartD
• /
• v.13D no.2 s.105
• /
• pp.215-222
• /
• 2006

The importance of mobile software test is being addressed to improve the productivity and reliability of the software. Test automation technique based on mobile platform is required for effective application of mobile software test. That is, a technique is needed to generate test case for mobile platform API. When test case generated, software productivity and reliability are improved, while test duration and cost are decreased. In this paper, we identified test case generation scope through previous works about test automation, suggested keyword driven method, a test case generation technique on J2ME platform, and recognized that proposed method can be applicable to generating test case based on J2ME platform.

• Journal of the Korean Society for Advanced Composite Structures
• /
• v.1 no.1
• /
• pp.16-26
• /
• 2010

In this paper, we present the result of investigations pertaining to the development of the floating type photovoltaic energy generation system. Pultruded FRP has superior mechanical and physical properties compared with those of conventional structural materials. Since the FRP has an excellent corrosion-resistance and high specific strength and stiffness, the FRP material may be highly appreciated for the development of the floating type photovoltaic energy generation system. In the paper, we discussed the development concepts of the floating type photovoltaic energy generation system, briefly. The mechanical properties of the FRP structural member used in the development are investigated through the tensile and compression tests. Test results are used in the finite element analysis and the design of the system. In addition, bolted connections of the members are briefly discussed and the strengths of FRP bolted connections are estimated based on the results of experiments. The experimental results are compared with the finite element analysis results and discussed briefly. The floating type photovoltaic energy generation system is designed, fabricated, and installed successfully in site.

• Proceedings of the Korean Operations and Management Science Society Conference
• /
• 2004.05a
• /
• pp.603-606
• /
• 2004

Automatic test case generation for testing an embedded software is considered. Existing tools for test case generation such as finite state machine or mutant test usually adopt top down approach and depend upon graphical transition and decision table, which makes it difficult to find out where the bugs exist. Also it is hard to describe the special features of embedded systems such as concurrent execution of individual components. Most of embedded systems interacts with the real world, receiving signals through sensors or switches and sending output signals to actuators that somehow manipulate the environment. Embedded software controls the entire system based on the logics such as interpreting the sensor inputs and making the actuators to start or stop their intended operation. This study proposes an automatic test case generation procedure that tests the system starting from the control logics of sensors, switches and actuators and then their concurrent execution controls, and finally the entire system operation. Such a stepwise approach makes it easy to generate test cases to tell where the bugs of embedded software exist.

• KIPS Transactions on Software and Data Engineering
• /
• v.2 no.7
• /
• pp.451-460
• /
• 2013

In order to achieve high test coverage, it is usual to generate test data using various techniques including symbolic execution, data flow analysis or constraints solving. Recently, a technique for automated test data generation that fulfills high coverage effectively without those sophisticated means has been proposed. However, the technique shows its weakness in the generation of test data that leads to high coverage for programs having branch conditions where different memory locations are binded during execution. For certain programs with flag conditions, in particular, high coverage can not be achieved because specific branches are not executed. To address the problem, this paper presents dynamic branch coverage criteria and a test data generation technique based on the notion of dynamic branch. It is shown that the proposed technique compared to the previous approach is more effective by conducting experiments involving programs with flag conditions.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.4
• /
• pp.30-37
• /
• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.