• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.160-165
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• 2022

This paper proposes an efficient method of reconstructing interconnections when the terminals of each plane change in real-time situations where randomly divided planes are interconnected. To connect all terminals when the terminals of each plane are changed, we usually reconstruct the interconnections between all terminals. This ensures a minimum connection length, but it takes considerable time to reconstruct the interconnection for the entire terminal. This paper proposes a solution to obtain an optimal tree close to the minimum spanning tree (MST) in a short time. The construction of interconnections has been used in various design-related areas, from networks to architecture. One of these areas is an ad hoc network that only consists of mobile hosts and communicates with each other without a fixed wired network. Each host of an ad hoc network may appear or disappear frequently. Therefore, the heuristic proposed in this paper may expect various cost savings through faster interconnection reconstruction using the given information in situations where the connection target is changing.

• Journal of information and communication convergence engineering
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• v.19 no.2
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• pp.114-119
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• 2021

This paper proposes a method to find an optimal T' with the most terminal of the subset of T' trees that can be connected by a given length by improving a memetic genetic algorithm within several constraints, when the set of terminal T is given to the Euclidean plane R². Constraint (1) is that a given length cannot connect all terminals of T, and (2) considers only the rectilinear layout of the edge connecting each terminal. The construction of interconnections has been used in various design-related areas, from network to architecture. Among these areas, there are cases where only the rectilinear layout is considered, such as wiring paths in the computer network and VLSI design, network design, and circuit connection length estimation in standard cell deployment. Therefore, the heuristics proposed in this paper are expected to provide various cost savings in the rectilinear layout.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.90-95
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• 2022

This paper proposes a method to find a tree with the maximum number of terminals that can be connected by a given length when numerous terminals distributed in a cluster form are given to the Euclidean plane R2 with several constraints. First constraint is that a given terminal is distributed in a cluster form, second is that a given length cannot connect all terminals in the tree, and third is that there is no curved connection between each terminal. This paper proposes a method to establish more efficient interconnections within terminals distributed in a cluster form by improving a randomly distributed memetic genetic algorithm. The construction of interconnections has been extensively used in design-related fields, from networking to architecture. Additionally, in real life, the construction of interconnections is mostly distributed in the form of clusters. Therefore, the heuristic algorithm proposed in this paper can be effectively utilized in real life and is expected to provide various cost savings.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.9
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• pp.1674-1680
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• 2009

This paper proposes an autonomous fault determination, fault zone isolation and fault restoration strategy based on the ethernet communication as a new attempt to solve the problem the of the existing central control method. In proposed method, The FRTU(Feeder Remote Terminal Unit)s on the feeder determines autonomously where the faulted zone is by exchanging the voltage and current information with neighbor FRTUs based on the network communication, and then separates the faulted zone in an nil-voltage status to make the protective device to reclose successively. In particular, the minimization of outage time and relational load balancing is archived by each interconnection switch which determines autonomously the load zone to be allocated among those zones after the sound outage zones was separated individually. Finally, to show effectiveness of the proposed fault restoration strategy, the several fault cases are simulated for the test distribution system, and the load balancing index of the proposed solution is compared with all of feasible solutions.